This section describes how to prepare for timing simulation by exporting the timing simulation netlist from Design Manager and creating the VSM netlist.
To export the timing simulation netlist from Design Manager, create an annotated NGD file, create a new EDIF file, and then read in the EDIF netlist. This section describes these steps.
To prepare for timing simulation of a Xilinx design, you must first use the Xilinx Design Manager and Flow Engine to produce and export timing simulation data for the design version and revision you want to simulate. The Flow Engine calls two programs you can run by selecting two options.
First, create the timing simulation data with NGDAnno, accessed in the Options dialog box.
NGDAnno does not apply to CPLD devices, so do not use it with those families.
To open the Options dialog box from the Flow Engine, select Setup
Options. You can also choose this template from Design Manager when you select Design Implement, then click on the Options button. This dialog box appears in next figure.
Figure 6.1 Options Dialog Box |  |
Click on the “Produce Timing Simulation Data” checkbox to add a new step called “Timing” to the Flow Engine when it runs.
Run NGD2EDIF to create an EDIF file. You can also access NGD2EDIF from the Options dialog box. by clicking on the Edit Template... button to the right of the Implementation title and then selecting the Interface tab. In the Simulation Data Options section, use the pulldown tabs to set the following two fields.
The following figure illustrates this dialog box.
Figure 6.2 Implementation Options Dialog Box | |
Click on OK to accept these implementation options close the Options dialog box.
These settings run NGD2EDIF, which takes the NGD file with timing information created by NGDAnno and exports it to a Viewlogic-compatible EDIF netlist.
The EDIF gets the name time_sim.edn, not the original design name, to avoid overwriting the original EDIF netlist and the original WIR file(s) produced in the next step.
After the design has been placed and routed, read the new EDIF file back into the Workview Office environment. using Viewlogic's EDIFNETI. In ViewDraw, select Tools Read Xilinx Timing EDIF to read in the time_sim.edn file.
As an alternate method of reading in the EDIF file with the timing information, use the EDIF Interfaces GUI. Click on the EDIF icon from the Workview Office Toolbar and select the “EDIF Netlist Reader” tab.
Fill in only the Input field if the EDIF file resides in the project directory. Use the Browse button if necessary. If the EDIF file resides in another directory, fill in the Output field with the path to your project directory.
The EDIF Netlist Reader looks similar to the next figure at this point.
Figure 6.3 EDIF Netlist Reader | |
Click on Apply to read in the time_sim.edn file.
You can also enter the following on the command line.
edifneti time_sim.edn
This program reads the EDIF netlist exported by the Xilinx Design Manager, and produces WIR files to represent the design. Because the EDIF netlist is hierarchical, EDIFNETI generates one WIR file for each level of hierarchy. Lower-level WIR files are named xba1.1, xba2.1 and so on, to avoid conflicts with the original design WIR files.
Next, in ViewDraw, select Tools Create Digital Netlist, or from the Workview Office Toolbar, select the VSM icon, illustrated in the following figure.
Either of the previous options opens the ViewSim Wirelister. Follow the following steps to create a timing simulation netlist from the time_sim.edn file.
Do not select the design.1 or design.edn file as the input, as this uses the uncompiled schematic design instead of the compiled version just created.
At this point, the ViewSim Wirelister should appear similar to the next figure.
Figure 6.4 Completed ViewSim Wirelister | |
This Viewlogic program reads the WIR files generated by EDIFNETI and produces a single VSM file for use by Viewsim.
This produces a time_sim.vsm file. Because the name of this file differs from the name of the original schematic, you need to tell Viewsim which schematic to annotate. See the “Annotating Values to Original Schematic” section for details.
