Do not leave unused inputs on symbols unconnected. You should never assume a default value for any unconnected symbol input except basic logic gates such as AND or OR. In some cases, an unconnected control input to a library symbol causes resulting behavior different from that of an input tied either High or Low. For example, with an unconnected CE input of an FDRE component, the CE logic that selects between the D-input and Q-feedback is removed. The flip-flop loads the value of the D-input ORed with its Q-feedback, clearly not the intended functionality. Timing simulation exhibits this resulting incorrect behavior; functional simulation propagates unknown signal values (X's).
Tie unused inputs to a constant High or Low logic level in the schematic. Use the VCC or GND symbol from the Xilinx family library (not the builtin library) to tie a net to a constant logic High or Low. As an alternative, you can specify a constant High or Low value by connecting a net on the component input pin and then labeling the net as “VDD” or “GND,” global names recognized by both Viewlogic and Xilinx software.
