This tutorial provided files that demonstrate the simulation capabilities of the Viewlogic software. These command (CMD) files contain directives and simulation vectors you can use in ViewSim, the Viewlogic gate-level simulator.
Slight differences exist between the command files for Functional Simulation (calc_4kf.cmd and calc_9kf.cmd) and the command files for Timing Simulation (calc_4kt.cmd and calc_9kt.cmd). The files have text that explain the differences.
If the design consists entirely of schematic elements, as described in “Functionally Simulating Category B Designs” section of the “Functional Simulation” chapter, you can easily run a functional simulation. Select Tools
Create Digital Netlist in ViewDraw and fill in the fields as shown in the following figure. Use this flow for the XC9500 version of the Calc design, as it meets the criteria for Category B.
Figure 8.55 ViewSim Wirelister for Category B Designs |  |
However, the XC4000E version of the Calc design contains RAM with initial values, so this design falls into Category A. You must compile the design with NGDBUILD and bring it back into Workview Office before simulating it. To simplify this process, use the Xilinx Functional Simulation GUI.
Part of the installation and setup process included running the custmenu command. This command set up contains five menu choices in ViewDraw, including one entitled “Xilinx Functional Simulation.” With the Calc design open in ViewDraw, select this menu item. When the GUI opens, select the family for this design and click on OK.
The Functional Simulation GUI runs the following five programs.
The Functional Simulation GUI produces a func_sim.vsm file. Because the name of this file differs from the name of the original schematic, you need to tell Viewsim which schematic to annotate. Use the schemnam command within the command file to do this.
After creating the func_sim.vsm file, open ViewSim by clicking on the ViewSim icon shown in the next figure. Keep the Calc schematic open in ViewDraw.
Select File Load ViewSim Netlist and choose func_sim.vsm to read in the simulation netlist. Next, select File Run Command File and choose calc_4kf.cmd. This runs the command file and launces ViewTrace (due to the “wave” command in the command file).
After implementing the design and timing it in the Flow Engine, bring the timing simulation netlist t back into Workview Office for a timing simulation. This file, time_sim.edn, reads back into the Viewlogic environment using the EDIF Netlist Reader (EDIFNETI).
From the Calc schematic in ViewDraw, select Tools Read Xilinx Timing EDIF. When this completes, close the command window and select Tools Create Digital Netlist. Follow these steps to create a timing simulation netlist from the time_sim.1 wire file.
Do not select the calc.1 or calc.edn file as the input, as this uses the uncompiled schematic design instead of the compiled version that you just created.
At this point, the ViewSim Wirelister appears, similar to the following illustration.
Figure 8.56 Completed ViewSim Wirelister | |
This Viewlogic program reads the WIR files generated by EDIFNETI and produces a single VSM file, for use by Viewsim. With the options selected, ViewSim launches and the command file runs. This flow is identical for both the XC4000E and XC9500 tutorial designs, with the lone exception of the unique timing simulation command files.
