VHDL Designs

Each design has two parts; an entity specification and architecture.

• Entity specification - defines the design's inputs and outputs.
  
  It is the design's external interface.
  
  The design can only have one entity specification (interface).
  
  
• Architecture - determines the entity's function.
  
  It is the design's internal implementation.
  
  The design can have multiple architectures (implementations).
  
  

The design's configuration specifies which architecture to use when an entity is compiled into a hardware design.

You can describe a VHDL design in separate VHDL source files or in one VHDL source file. Each file contains entities, architectures, or packages. Packages define global information that can be used by several entities. You can often reuse VHDL design files in later design projects.

The following figure shows a block diagram of a VHDL design's hierarchical organization into files.

Figure 3.1 Design Organization