Mapping Subprograms to Components (Entities)

In VHDL, entities cannot be invoked from within behavioral code. Procedures and functions cannot exist as entities (components) but must be represented by gates. You can overcome this limitation with the compiler directive map_to_entity, which directs Foundation Express to implement a function or procedure as a component instantiation. Procedures and functions that use map_to_entity are represented as components in designs in which they are called.

You can also use the Foundation Express Implementation GUI to create a new level of hierarchy from a VHDL subprogram, as described in the Foundation Express online help.

When you add a map_to_entity directive to a subprogram definition, Foundation Express assumes the existence of an entity with the identified name and the same interface. Foundation Express does not check this assumption until it links the parent design. The matching entity must have the same input and output port names. If the subprogram is a function, you must also provide a return_port_name directive, where the matching entity has an output port of the same name.

These two directives are called component implication directives.

-- pragma map_to_entity    entity_name
-- pragma return_port_name port_name

Insert these directives after the function or procedure definition.The following example shows how to insert these directives.

function MUX_FUNC(A,B: in TWO_BIT; C: in BIT) return TWO_BIT is

-- pragma map_to_entity MUX_ENTITY -- pragma return_port_name Z ...

When Foundation Express encounters the map_to_entity directive, it parses but ignores the contents of the subprogram definition. Use --- pragma translate_off and -- pragma translate_on to hide simulation-specific constructs in a map_to_entity subprogram.

NOTE

The matching entity (entity_name) does not need to be written in VHDL. It can be in any format that Foundation Express supports.

WARNING

The behavioral description of the subprogram is not checked against the functionality of the entity overloading it. Presynthesis and post-synthesis simulation results might not match if differences in functionality exist between the VHDL subprogram and the overloaded entity.

The following example shows how to use component implication directives on a function. The resulting circuit follows the example.

package MY_PACK is
     subtype TWO_BIT is BIT_VECTOR(1 to 2);
     function MUX_FUNC(A,B: in TWO_BIT; C: in BIT) return
                TWO_BIT;
end;

package body MY_PACK is

     function MUX_FUNC(A,B: in TWO_BIT; C: in BIT) return
                TWO_BIT is

     -- pragma map_to_entity MUX_ENTITY
     -- pragma return_port_name Z

     -- contents of this function are ignored but should
     -- match the functionality of the module MUX_ENTITY
     -- so pre- and post simulation will match
  begin
       if(C = '1') then
            return(A);
       else 
            return(B);
       end if;
   end;

end;

use WORK.MY_PACK.ALL;

entity TEST is
     port(A: in TWO_BIT; C: in BIT; TEST_OUT: out TWO_BIT);
end;

architecture ARCH of TEST is
begin
     process
     begin
          TEST_OUT <= MUX_FUNC(not A, A, C); 
                                          -- Component implication call
     end process;
end;
use WORK.MY_PACK.ALL;

-- the following entity 'overloads' the function
-- MUX_FUNC above

entity MUX_ENTITY is
     port(A, B: in TWO_BIT; C: in BIT; Z: out TWO_BIT);
end;

architecture ARCH of MUX_ENTITY is
begin
     process
     begin
            case C is
                   when '1' => Z <= A;
                   when '0' => Z <= B;
            end case;
     end process;
end;

Figure 6.10 Circuit for Using Component Implication Directives on a Function

The following example shows the same design as the previous example but without the creation of an entity for the function. The compiler directives have been removed. The resulting circuit is shown in the figure following the example.

package MY_PACK is
     subtype TWO_BIT is BIT_VECTOR(1 to 2);
     function MUX_FUNC(A,B: in TWO_BIT; C: in BIT) 
            return TWO_BIT;
end;

package body MY_PACK is

     function MUX_FUNC(A,B: in TWO_BIT; C: in BIT) 
            return TWO_BIT is
     begin
          if(C = '1') then
               return(A);
          else 
               return(B);
          end if;
     end;
end;

use WORK.MY_PACK.ALL;

entity TEST is
     port(A: in TWO_BIT; C: in BIT; Z: out TWO_BIT);
end;

architecture ARCH of TEST is
begin
     process
     begin
          Z <= MUX_FUNC(not A, A, C); 
     end process;
end;