목차
Useful Design Guide To Make the PLD
Xilinx FPGA Gate Count
First Order Size Estimate
Consider Architecture
Functions of 4 inputs are best
Why Use to Hierarchy
Hierarchy Guidelines
Locking I/O Pins
Use Legal and Readable Names
Synchronous Design
Glitches
Avoid Gated Clock and Reset
Use Clock Enables
Clock Skew
Asynchronous Logic
Safely Synchronising Design for
Asynchronous Inputs
Performance Estimation
Pipeline Logic
State Machines Three Types
State Machines
State Machine Design Tips
Duplicate Registers
Duplicate Combinatorial Logic
LAYOUT: Pin Selection I
LAYOUT: Pin Selection II
LAYOUT: Pin Selection III
LAYOUT: Pin Selection IV
LAYOUT: CCLK
LAYOUT: Debug Tips
LAYOUT: Debug Tips
Xilinx Product Strategy
PPT 슬라이드
PPT 슬라이드
4000 Series X = EX/XL/XV
XC4000X Family Features
XC4000X Series High Density
Xilinx FPGA Comparison
XC4000XL Footprint and Packaging
Density: The Facts
PPT 슬라이드
PPT 슬라이드
PPT 슬라이드
PPT 슬라이드
XC4000X VersaRingTM
0.35? FPGA, 5 Volt Compatible
High Performance 0.35u FPGAs 3.3 volts
in 1997
XC4000XL Delivers High Performance at
3.3 V
FPGAs Overlap Gate Array Design Starts
XC4000XL Performance Overlaps with
Gate Arrays
XC4000XL Family
XC4000XL Success Story
XC4000XL Success Story
World’s... First 0.25 micron FPGA, First
250,000+ Gate FPGA, First 2.5 Volt
FPGA, First 25 million transistor logic
device
Technology Leadership: XC4000XV Family
World’s Most Advanced Logic Devices
Xilinx FPGA Density Leadership XC4000XV
Production Roadmap
0.25? FPGA, 5 Volt Compatible
High Performance 0.25? FPGAs 1997/1998
The XC4000XV - 0.25 μm Fast
4KXV Addresses 90% ASIC Starts by
Speed
Xilinx: The Density Leader
XC4000XV Family
Foundation FPGA Express
Foundation Express Features
Xilinx-Express Design Flow
Express Input and Output
Express Design Process (1)
Create a Project
Analyze the Design (1)
Analyze the Design (2)
Implement the Design
Check for Errors and Warnings
Define Clock Period
Define Global Synchronous Delays (1)
Define Global Synchronous Delays (2)
Define Individual Synchronous Delays
Define Key Port Features (1)
Define Key Port Features (2)
Control the Hierarchy (1)
Control the Hierarchy (2)
Optimize the Design
View Results
Verify Results (1)
Verify Results (2)
Verify Results (3)
Export Netlist |