Locking I/O Pins

• Avoid it until the last possible iteration

  • Or until design is 75-80% complete & timing requirements met
  • More flexibility on board than inside FPGA
  • Then re-align I/Os in logical pattern with minimal movement

• Specify edge locations only to guide layout

  • If schematic is entered, let place & route choose I/O locations
  • Useful for partial designs or incremental design

이전 슬라이드

다음 슬라이드

첫 슬라이드로 이동

그래픽 버전 보기