Performance Estimation
Use block delays as estimate of net delays
Use desired clock frequency to determine allowed CLB depth
- Compare to functional requirements and modify design to meet performance needs
Example for 50 MHz clock frequency in XC4000XL-3:
- Clock period 20 ns
- One level - 8 ns (tCO + tNET + tSU)
- Delay allowance 12 ns
- Each added level div 6 ns (tPD + tNET)
- Added levels of logic allowed 2 CLBs