Express Input and Output

• Input files may be VHDL or Verilog format

  • Mixed Verilog/VHDL modules are accepted
  • Schematics may also be used, but should not be input into Express
  • Schematic files in XNF or EDIF format will be merged into the design in Xilinx Design Manager

• Output netlists are in XNF format

• Timing Specifications may be specified in Express

  • Timing Specifications are not used during Synthesis
  • Timing Specifications can be included in the output netlist

Reports

Timing

Requirements

VHDL

Verilog

Express

.XNF

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