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*Standard Interface Netlist Format
** Standard Delay Format
Schematic Entry
OrCAD/ESP
Design Environment
Place & Route
PAR (Place & Route)
Functional Simulation
OrCAD Simulate
XSimMake
*SDF
Netlist
(XNF or *EDIF)
Implementation Tools
ABEL HDL
LogiBlox
LogiCores
Optional
XNF modules
(Created by HDL
Synthesis tools)
VHDL,
*XNF
Design Flow
M1
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