Multi-Source IntegrationMixed-Level Flows

Check Point Verification

EDIF

VHDL

Verilog

SDF

Knowledge

Driven Implementation

HDL

Schematic

Existing Designs

StandardsBased

• Enables Multiple Sources and Multiple EDA Vendors in the Same Flow

• Allows Team Development

• Reduces Design Source Translations

• Design the way you are used to

• Enables Rapid, Accurate Iterations

• Works Well Within Existing ASIC Flows

• Facilitates Design Reuse

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