The SDF File

• Standard Delay Format

  • Separate file used to specify design timing (delays) to VHDL and Verilog simulators
  • A1.4 Supports SDF version 2.1

• Automatically generated by NGD2VHDL or NGD2VER

  • Post-Map simulations - Contains block delays only, no routing
  • Post Place and Route - Contains all block and routing delays

• Must be specified to simulator

  • Verilog - Automatically read in due to $sdf_annotate function or is specified from a command line or GUI switch
  • VHDL - Must specify SDF file from a command line or GUI switch

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