Composite Input / Output Timing
Clock
PCI
Speedway
t su = 7 nsec
t h = 0 nsec
t ckq + t on
t val
t su
11 nsec
t del + t skew
12 nsec
7 nsec
Clock
Time delays
30 nsec
t val = 11 nsec
40% of cycle time is lost to signal and clock distribution
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