CPLD and FPGA
Architecture PAL/22V10-like Gate array-like
More Combinational More Registers + RAM
Basic Cell Product Term CLB & LUT
Density Low-to-medium Medium-to-high
0.5-10K logic gates 1K to 1M system gates
Application Combination based Register Based
Timing Delay Predictable timing Application dependent
Performance Predictable timing Application dependent
Up to 250 MHz today Up to 150MHz today
Interconnect “Crossbar Switch” Incremental
Complex Programmable Logic Device Field-Programmable Gate Array