Design Flow
Design Entry in schematic, ABEL, VHDL, and/or Verilog. Vendors include Synopsys, Aldec (Xilinx Foundation), Mentor, Cadence, Viewlogic, and 35 others.
Implementation includes Placement & Routing and bitstream generation using Xilinx’s M1 Technology. Also, analyze timing, view layout, and more.
Download directly to the Xilinx
unlimited reconfigurations* !!
*XC9500 has 20,000 write/erase cycles