XC9500XLSystem Designer’s CPLD
2.5V/3.3V/5V I/O Capability
Invertible Local & Global P-Term Clocks and OEs
Common ISP/JTAG Support for CPLDs/FPGAs
Superior connectivity & performance
Better control of board & system signals during ISP
Easy multi-voltage interfacing
Max number of clock & OE options
Improves noise margin; better slow
Totally controlled board initialization
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