목차
Programmable Logic Training Course HDL Editor
HDL Entry Editor
Language Assistant
Synthesis Options
Programmable Logic Training Course State Editor
Create FSMs Graphically
Creating State Machine (FSM)
After FSM Entry...
Machine Properties
Programmable Logic Training Course Simulator
Waveform Viewer
Inserting Probes
SC Probes Box
Component Selector
Stimulator Selector
Displaying Buses
Programmable Logic Training Course Design Manager
Design Flow for Implementation
Step 1: Invoke Design Manager
Step 1: Invoke Design Manager
Step 2: Start a New Project
Step 2: Start a Project (cont.)
Step 3: Specify Back Annotation
Step 4: Implement the Design
Step 5. Check Results
Step 6: Configure the FPGA/CPLD
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