목차
PPT 슬라이드
1999 Designs Demand...
Traditional Multi-Chip Boards
Multi-Chip Board Problems
The FPGA Solution
DLLs Maximize I/O Speed
Virtex Has 4 Independent DLLs
LVTTL Data Rate with DLL
Other DLL Functions
Duty Cycle Correction
Clock Doubling and Mirroring
Precise Clock Mirroring
Clock Division
Multi-Standard SelectI/O
Mix & Match Output Standards
Mix & Match Input Standards
SSTL Clock-to-Out With DLL
SSTL Data Rate with DLL
From FPGA to System Component ‘Redefining the FPGA’
Power and Thermal Issues
Virtex Power Consumption
Thermal Management
Power Supply Decoupling
Virtex Configuration
Volts, Amps, and Watts: Recap
Spending the 10 ns Budget
You Don’t Have To Be An Expert
Virtex CLB
Fast Function Generators
Connecting Function Generators
Fast Local Routing
Use Pipelining for Speed
16-Bit Pipeline in One LUT
Fast Logic Needs Fast Routing
Go Farther, Faster
No Routing Congestion
Built-in Tri-State Busses
Arithmetic ? A Special Case
Wide Arithmetic
Fast Address Decoders
Speed Is Never Wasted
Creating a High-Speed Clock
Optimized for the Future
10 ns is Long Enough
Implement Designs Automatic
100+ MHz Memory
Data Storage Hierarchy
SelectRAM+
Block SelectRAM+
High-Speed Memory Interfaces
Input/Output Data Buffers
Dual-ported I/O Buffers
Ping Pong Buffers
Small FIFOs in SRLUTs
Large FIFOs in Block RAM
Pre-computing for Speed
Multiplication By A Constant
16-bit Scaler
Changing the Constant
Large Function Tables
Block RAM/ROM Creation
Memory Summary
Designing for 100+ MHz
The Virtex Family
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