Master Parallel Mode

• FPGA automatically loads itself from external byte-wide PROM

  • Can use part of existing PROM

• Internal CCLK clocks address counter in FPGA

  • Up from 0 or Down from all 1’s, specified by mode
  • 16-22 bit address for large FPGA, or large daisy chain

• Data is still serialized internally (configures at same rate)

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