PPT 슬라이드
Serial Distributed Arithmetic
- Parallel In, Parallel Out, Bit-Serial Internally
- All taps processed in parallel
- Full precession through entire core
- One clock cycle required for each data bit
- One additional clock cycle for symmetric filters
EXAMPLE: 10-bit data, 80 taps, symmetrical FIR:
- For a bit level clock = 90 MHz
- Max sample rate = 90 MHz / 11 clks = 8.2 Million samples/sec.
- Process 80 taps every 122 nsec.
- 656 Million MACs, 257 CLBs, 2.55 Million MACs / CLB