Joining the Cores

Here VHDL is used to link the cores into a system. Schematic symbols may also be used.

skip_value: skip_val --The integrator for skipping through the Sine table with forcing constant

port map (cb => skip_constant);

skip_integrater: skip_int

port map (b => skip_constant,

s => skip_integrate,

l => GND,

ce => VCC,

c => clk);

form_sine_address:

for i in 0 to 6 generate --extract 7 bits required to address look-up table

--MSB is not used as this represents overflow.

--Lower bits are internal precision for integrator.

skip_address (i) <= skip_integrate(i+10);

end generate form_sine_address;

sine_table : sine_lut -- sine wave look-up table

port map (theta => skip_address,

output => sine_wave,

ctrl => VCC, --select SINE output when high

c => clk);

All component declaration and

port map code provided by Coregen