Controlling Initial States in VHDL or Verilog

Use the INIT attribute in the UCF file to control the initial value of macrocell registers during device power up. Use the value “S” to Set on power-up; use “R” to Reset on power-up. (Reset is the default.)

In the UCF file, apply the INIT attribute to the nets of flip-flops inferred or instantiated in your HDL design.

net net_name INIT=R|S;

For example, if your HDL design contains a clocked scalar signal “myflop” and a clocked vector signal “mycounter” with range 7 down to 0, the syntax of the INIT attribute is:

NET myflop INIT=S;

NET mycounter_* INIT=S;