Creating Bidirectional Signals Using VHDL

The following code shows how to implement bidirectional signals in VHDL:

process (clk) begin

if clk’event and clk=‘1’ then

out0_int <= data0;
-- clock data into register

end if;

end process;

out0 <= out0_int when enable=‘1’ else ‘Z’;

-- Drive I/O pin when enable is high

out1 <= out0_int xor out0;

-- out1 goes high when out0 reg. and pin are different