Multiplexing Output Signals in Verilog

The following code shows how to multiplex signals in Verilog:

// Using macrocell logic for a conventional multiplexer:
always@(A or SEL or B or C or D)

begin
case(SEL)
00:

muxout=A;

01:

muxout=B;

10:

muxout=C;

11:

muxout=D;

endcase
end

// Using 3-state outputs to multiplex registers fast
always@(posedge CLK)

begin

REG_A = DATA_A;
REG_B =DATA_B;

end

assign DOUT_A = (SEL ==0)?REG_A:1'bz;
assign DOUT_B = (SEL ==1)?REG_B:1'bz;