Multiplexing Output Signals in VHDL

The following code shows how to multiplex signals in VHDL:

-- Using macrocell logic for a conventional multiplexer:
process (SEL, A, B, C, D)
begin

case SEL is

when "00" => MUX_OUT <= A;
when "01" => MUX_OUT <= B;
when "10" => MUX_OUT <= C;
when "11" => MUX_OUT <= D;

end case;

end process;
-- Using 3-state outputs to multiplex registers fast
process (CLK)
begin

if CLK'event and CLK='1' then --CLK rising edge

REG_A <= DATA_A;
REG_B <= DATA_B;

end if;

end process;
DOUT_A <= REG_A when SELECT='0' else 'Z';
DOUT_B <= REG_B when SELECT='1' else 'Z';

--Tie output pins DOUT_A and DOUT_B together off-chip.