When targeting an XC9500XL or XC9500XV device, logic connected to the clock enable (CE) input of a FDCE or FDPE primitive in your design will only be implemented using the clock enable p-term of the XC9500XL or XC9500XV macrocell when the logic can be completely implemented using a single p-term. Only the FDCE and FDPE primitives use the clock enable p-term.

If you have a CPLD design containing FDCE or FDPE flop primitives and you want to prevent the Fitter from using the clock enable p-term in the XC9500XL or XC9500XV macrocell, you should replace the flop primitive with an FDCP primitive or use the FDCPE macro, each of which does not allow the clock enable p-term to be used. The FDCPE component is a macro which always gets expanded into a simple D-type flip-flop with its Q-feedback multiplexed into its D-input; the clock enable p-term is not used. After substitution, the unconnected PRE or CLR input to the FDCPE will be automatically trimmed away by the CPLD fitter.

If you have a CPLD design containing FDCE or FDPE primitives and you want to force the logic connected to the CE input of the components to be implemented using the clock enable p-term in the XC9500XL or XC9500XV macrocell, you can apply the REG=CE attribute on the FDCE or FDPE instance or its output net. This will force the fitter to use the CE pin. If you force the useage of the CE pin you may find that the logic connected to the clock enable input on those components may not get optimized into the same macrocell as the flip-flop. The XC9500XL and XC9500XV macrocells contain only a single product-term to implement clock enable input logic. The CPLD fitter does not attempt to transform your clock enable input logic onto the D-input of the flip-flop if it cannot be completely implemented using the clock enable p-term. In general, only primary inputs (device input pins or macrocell feedbacks), their complements or positive-logic AND-gate functions of primary inputs or their complements can be completely implemented using the p-term. If you connect a more complex logic function to the clock enable input of an FDCE or FDPE component and it does not get completely implemented on the clock enable p-term, your design may incur extra macrocell resources and combinational macrocell feedback delays. Useage of the REG=CE attribute when targeting XC9500 devices has no effect.