Creating Readback Registers in Verilog

The following code shows how to create a readback register using Verilog

always@(posedge clk)

begin
if(write_enable)

data_reg_int = data_reg;
//write data from the I/O pin into the register

end

assign data_reg = (read_enable==1)?data_reg_int:1'bz;
//Drive I/O pin when read_enable is high