Fast and Slow Attribute in VHDL or Verilog

In VHDL or Verilog designs, apply the FAST or SLOW attribute to an output pad net in the UCF file using the following syntax:

NET net_name FAST | SLOW;

When assigning slew rates to bus (vector) elements, the name generated in the netlist will be the bus name and subscript seperated by an underscore. For example if the design contined a bus Q with subsripts 3 downto 0, then you would use Q_3 as the net name in the UCF to assign a slew rate to subscript 3 of Q.