Indirectly Specifying tSU

You can indirectly specify the tSU (setup-to-clock) for all inputs in your design relative to a flip-flop using a Pad-to-Setup timespec.

Pad-to-Setup paths start at input pads, propagate through input buffers and any number of combinatorial logic levels before ending at a flip-flop D/T input and includes the receiving flip-flop’s tSU. Pad-to-Setup paths do not propagate through flip-flops. These paths are also broken at bidirectional pins. Pad-to-Setup paths do not take into account the clock path delay from the clock pad to the flip-flop, so you must determine the clock delay when deriving the Pad-to-Setup timing value.

To specify tSU, use the clock path delay from the device data sheets and calculate the Pad-to-Setup delay to be used as the value in the timing constraint with the following equation for global clocks:

Pad-to-Setup Value = desired tSU + tGCK

Use the following equation for product term clocks:

Pad-to-Setup Value = desired tSU + (tIN + tPTCK)

The format of the Pad-to-Setup timespec is:

TSnn=FROM:data_input_pad:TO:flip_flop_group:pad_to_setup_value

For example, if you need an external tSU of no more than 7.5 ns for all inputs to an XC95108-10 global clock tGCLK= 3ns), use the following timing constraint:

TS01=FROM:PADS:TO:FFS:10.5

If you need an external tSU of no more than 3.5 ns for a specific input to a specific flip-flop clocked by a XC95108-10 product term clock (tIN = 3.5ns, tPTCK = 3.5), use the following timing constraint:

TS01=FROM:PADS(STROBE):TO:FFS(START):10.5

Entering Timespecs in a UCF File

Grouping Signals