Xilinx Property BUFG

Use BUFG to assign signals to Xilinx CPLD global nets with the following syntax:

xilinx property ‘BUFG={CLK|OE|SR} signal_list’;

CLK, OE, and SR indicate clock, output enable, or set/reset respectively.
For example, if you want to assign signals to the global clock nets, do the following:

xilinx property ‘BUFG=CLK clk0 clk1’;

To assign signals to the global output enable nets, do the following:

xilinx property ‘BUFG=OE oe0 oe1’;

To assign a signal to the XC9500 global set/reset net, do the following:

xilinx property ‘BUFG=SR reset’;