WebPACK CPLD_Fitter Release Notes

Version 2.1WP2.1

The following issues are known at the time of release:
  1. The device XC9536-6-CS48 appears in the device selection list of the Design Manager and runs as a valid target through the CPLD fitter. However there are currently no plans to make the -6 speed grade available for the XC9536-CS48 package. Please select the -5 or -7 speed grade instead.
  2. If you install WebPACK on the same PC as Xilinx Foundation software, the following conditions indicate that your system environment variables are not properly set when you try to run Foundation software. Refer to the CPLD_Fitter ReadMe file for instructions on how to switch your environment back to Foundation. If the problem persists, you may need to re-install your Foundation software.
  3. When applying a BUFG property to an internal net, the resulting global I/O pin driver is erroneously set to SLOW slew rate even when the default slew rate is set to FAST. To force FAST slew rate, create an I/O port in your design, pass the global control signal through the I/O port and apply the BUFG property to the I/O pad. Alternatively, create just an output port in your design connected to the global control signal source and apply the BUFG property to the internal net driven by the global control source (before the output buffer instance). (Xilinx reference number 116084.)
  4. The PROHIBIT property does not exclude pins from being connected to ground when the "Use Programmable Ground Pins" option is enabled. (Xilinx reference number 104919).
  5. The Timing Analyzer does not trace any paths that pass through the asynchronous clear or preset pins of flip-flops. This includes the data and latch-enable inputs of transparent latch primitives (all inferred latches in VHDL/Verilog, .LE and .LH extensions in ABEL, or the LD schematic primitive), which are implemented using the CLR and PRE inputs of a macrocell flip-flop with grounded clock. Such paths are not reported in the Timing Report and are not considered for timing-driven (timespec) optimization.
  6. The Timing Analyzer does not trace Clock enable paths (CE inputs to FDCE/FDPE primitives). The effects on setup time and clock frequency due to clock enable paths are not included in the Timing Report. (Xilinx reference number 115839.)
  7. The REG=CE property is not accepted in UCF files and causes the fatal error code "NgdHelpers:32 ". Currently, the REG property can only be specified in the design netlist itself. (Xilinx reference number 115897.)
  8. Binary-encoded FSMs (or other compact state encoding schemes) generally result in better performance in CPLD devices than one-hot FSMs.
  9. When using test vectors with a 9500XL/XV BG256 package a core dump will appear at the hprep6 stage. The only workaround for this package is to produce a jedec file without test vectors.
  10. When using the Constraints Editor, some timing constraints are generated that have extraneous quotes added around the signal qualifier in pattern match strings, which the CPLD Fitter does not recognize. For example if the UCF file contains:
      11. TIMEGRP "ADDR" = PADS("ADDR<*>");
      TIMESPEC "TS_ADDR_TO_A1_CS" = FROM "ADDR" TO "A1_CS" 10.000000 ns;
    The CPLD Fitter will issue a warning similar to the following:
      WARNING:hi429 - Cannot apply TIMESPEC TS_ADDR_TO_A1_CS = MAXDELAY:FROM:ADDR:TO:A1_CS:10.000000 nS because of one of the following: (a) a signal name was not found; (b) a signal was removed or renamed due to optimization; (c) there is no path between the FROM node and TO node in the TIMESPEC.
    Edit the UCF file and remove the quotes from just the signal qualifier as follows:
      TIMEGRP "ADDR" = PADS(ADDR<*>);
  11. When running the timing analyzer if the detailed report exceeds 2,000,000 paths then the editor will default to showing an empty report file.
  12. The OFFSET timespec property does not support the use of the TIMEGRP keyword for CPLD devices.
  13. When generating timing simulation output netlists, select only among the "Generic" forms of EDIF, VHDL and Verilog. Selecting any of the tool-specific forms may cause errors.
  14. When closing the Constraints Editor, a GPF error may occur with the application. Constraints Editor will still write the constraints file correctly and is not affected by the error.
  15. When the Programmer module is installed, the Design Manager GUI lists various FPGA families in the Part selection menu. Only the CPLD families (9500, 9500XL and 9500XV) can be selected for design implementation. The FPGA families that appear are only supported in the JTAG Programmer tool.
You can find additional technical issues that have been reported on the Xilinx CPLD Fitter in the CPLD Implementation Answers Listing section of the Xilinx Technical Support web page. Some of the issues listed there may not apply to the CPLD Fitter used in WebPACK.