WebPACK HDL_ABEL Release Notes

Version 2.1WP2.1

The following issues are known at the time of release:
  1. Do not run CoolRunner (XPLA) software or any software that contains a "Project Navigator" GUI, "ECS" schematic capture or ABEL compiler at the same time as this WebPACK software for XC9500-series devices. Individual processes or entire applications may lock up if they are both running at the same time. If you attempt to invoke WebPACK Project Navigator while any of these other conflicting applications is already running, an error message is displayed instructing you to close the other application.
  2. Some processes may fail with some form of an Application Error if the system path is longer than 120 characters after WebPACK is installed. You will need to shorten the path to less than 120 characters for these processes to work properly.
  3. The HDL_ABEL module requires that the operating system be rebooted after installation in order to set the PLS_HOME environment variable. If the system is not rebooted then you may experience error messages during an HDL flow such as:
      4. ERROR : File not found : part.err
  4. In order to preserve redundant logic terms in both VHDL and design implementation, apply the dont_optimize attribute to the logic you wish to preserve as follows:
      5. entity example is
      ...
      attribute dont_optimize : string;
      end example;
      architecture arch of example is
      ...
      attribute dont_optimize of net_name : signal is "yes";
      begin ...
       
  5. Project Navigator does not support long filenames (greater than 8 character base name or 3 characters extension) or filenames with embedded spaces. You may also encounter difficulty if the total path name to your project directory is too long.
  6. Binary-encoded FSMs (or other compact state encoding schemes) generally result in better performance in CPLD devices than one-hot FSMs. In ABEL designs, you must explicitly define the state vector values for each state in an encoded FSM. Using the symbolic state machine definition in ABEL will result in a one-hot FSM, which may impact your CPLD performance.
  7. Even though you can choose to add a VHDL test bench into your design under the Project Navigator interface, HDL simulation is not supported in this release of WebPACK.
  8. Project Navigator does not support VHDL files containing both entities and packages. To use a design that uses both packages and entities in Project Navigator, place the packages in a separate VHDL file and add the source file as a VHDL Package under Project Navigator.
  9. If you invoke a report viewer process when its parent process (fitter or compiler) is not completed, Proj Nav automatically runs the parent process. In this case, if the parent process encounters any fatal errors, the report file will be deleted before it can be viewed. To view the report file when errors occur, invoke (rerun) the parent process by itself. Then invoke the report viewer process after the parent process stops with its error.
  10. Project Navigator assumes that only the last entity in a VHDL design file can be the top level entity. To synthesize a low level entity, place the entity in a separate file and add the new source to your project. You can then select the low level entity and perform a check syntax or synthesize process on it.
  11. If a GPF error occurs while closing the Constraints Editor, a red X will be placed next to the process instead of the normal green check mark. The Constraints Editor will have completed writing the UCF file correctly even though Project Navigator indicates that it failed.
  12. If you are working on the Windows 98 platform, UCF files may not open properly when invoked from the source window of Project Navigator. To have the files loaded automatically when invoked from Project Navigator, manually associate the UCF file type to Notepad under Windows Explorer by double clicking on a UCF file in an open Explorer window and then choosing Notepad from the list window that appears. Make sure that "Always use this program to open this file" is checked before clicking the OK button.
  13. Remember that net names specified in the UCF file are case-sensitive, and the cases of your signal names in your HDL designs are preserved.
  14. The names you choose for your project name and entity or module names will determine the resultant file names in the design directory in the following ways:
ABEL-specific issues:
  1. The ABEL language has been enhanced to accept alphanumeric pin names, such as used on CSP and BGA type packages. Enclose alphanumeric pin names in 'single-quotes' in your PIN declaration statements. Refer to the PIN keyword in the ABEL Language reference in the WebPACK Help system for details.
  2. For all signals driving output pins, you should always refer to them with the appropriate dot-extension (.PIN, .FB, .Q, .COM) when using their feedback in other equations. Using an output pin signal name as feedback without dot-extension typically results in pin feedback being used.
  3. If you refer to a feedback or input-only signal inconsistently with regards to dot-extension, you may get a fatal error message about illegal use of .PIN or .COM extensions. The error message names only the first occurrence of an offending signal name. Inconsistent usage of dot-extension occurs when you refer to a signal name without extension and again with the .PIN or .COM extension, and both reference the same signal. The most common occurrence is when an input-only pin is referenced both with and without the .PIN extension.
  4. In your ABEL design, do not use identifiers that begin with the underscore character "_". Such names are illegal in EDIF netlists.
  5. In your ABEL design, do not use an identifier that ends with the underscore character "_" if the same name is also used without trailing underscore. During netlisting, intermediate net names are created which will collide for the two similar identifiers. Invalid connectivity may result without warning.
  6. If you are running a design that was previously run using the obsolete Xilinx Plusasm flow (such as in the old XABEL-CPLD product), the obsolete "xepld property" statements are no longer supported and will be ignored. Please refer to the Properties section of the ABEL Language reference in the WebPACK Help system. The obsolete Plusasm flow is not supported in WebPACK.
  7. When compiling some ABEL designs, the BLIFOPT step begins but never completes. Alternatively, blifopt completes but the blif2net step fails due to insufficient memory. One possible cause is that the design contains some arithmetic, comparator or decode logic that is either very large or is combined with other logic so that it becomes difficult to optimize. To work around this problem, insert the "@carry 2;" ABEL directive at the top of your declaration section or before the problematic equation. This will cause the ABEL compiler to break up the large equation into a number of smaller intermediate nodes, which can then be translated into EDIF more efficiently. The CPLD Fitter can still optimize the logic across the intermediate nodes.
  8. ABEL does not preserve buffer or simple inverter nodes. Any combinatorial equations consisting of simple buffers or inverters are always collapsed into adjacent equations before netlisting.

You can find additional technical issues that have been reported on the Xilinx ABEL interface in the XABEL Answers Listing section of the Xilinx Technical Support web page. Some of the issues listed there may not apply to the HDL compilers used in WebPACK.