Copyright: HH Bridge(c) Bristol Technology Inc. 1993


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Programming and Verification Overview

JTAG Programmer software uses sequences of JTAG instructions to perform the following programming and verification operations. The user need only select the desired operation; the software will execute all required JTAG commands transparently.

Device operation options available to users are:

Program. Downloads the contents of the JEDEC or BIT file to the device programming registers.

Verify. Reads back the contents of the device programming registers and compares them with the JEDEC or BIT file.

Erase. Clears device configuration information.

Functional Test. Applies user-specified functional vectors to CPLDs from the JEDEC file to the device using the JTAG INTEST instruction, comparing results obtained against expected values. Reports any differences to the user.

Blank Check. Checks whether a CPLD device has been programmed or is erased.

Readback Jedec. Reads back the contents of the CPLD's device programming registers and creates a new JEDEC file with the results.

Get Device ID. Reads the contents of the JTAG IDCODE register. Displays contents for the user.

Get Device Checksum. Reads back the contents of the CPLD's device programming registers and calculates a checksum for comparison against the expected value.

Get Device Signature/Usercode. This value is selected by the user during fitting. The specified value is translated to binary values in the JEDEC or BIT file. During device programming these values are loaded into the JTAG USERCODE register. This function reads the contents of the USERCODE register and displays the result.

Bypass. Ignores this device when addressing devices in the JTAG boundary scan chain. This option is only available through chain operations.

See Also

 "What is IEEE 1149.1?"

 "JTAG TAP Controller States"

 "JTAG Instructions Supported by Xilinx Devices"


User Feedback

When using the graphical user interface, immediate feedback is provided by a scrolling log file and alert boxes. Detailed information regarding failure is located in the system log file, and is provided for both the PC and workstation based tool.


Required Files

You need to provide JEDEC files for each XC9500/XL/XV CPLD device, BIT files for each Xilinx FPGA device in the JTAG programming chain, and BSDL files for the remaining devices.

JEDEC Files

JEDEC files are XC9500/XL/XV CPLD programming files generated by the Xilinx CPLD fitter. They are ASCII text files containing programming information and, optionally, functional test vectors that can be used to verify the correct functional behavior of the programmed device. One JEDEC file is required for each XC9500 device in the JTAG programming chain.

Use the device properties (File → Properties) dialog to specify the location of JEDEC files for each XC9500/XL/XV device. The required extension for JEDIC files is .jed.

BSDL Summary

The Boundary-Scan Description Language (BSDL) files use a subset of VHDL to describe the boundary scan features of a device. The JTAG Programmer automatically extracts the length of the instruction register from the BSDL file to place non-Xilinx devices in bypass mode. One user-provided BSDL file is required for each type of non-Xilinx device in the JTAG programming chain. Xilinx BSDL files are located automatically by the JTAG Programmer.

Use the device properties dialog to specify the location of BSDL files for non-Xilinx devices. The name of the BSDL file is assumed to be <device name>.bsd.

BIT Files

Bit files are Xilinx FPGA configuration files generated by the Xilinx FPGA design software. They are proprietary format binary files containing configuration information. One BIT file is required for each Xilinx FPGA in the JTAG boundary-scan chain.

Use the device properties (File → Properties) dialog to specify the location of the BIT files for each Xilinx FPGA device. The required extension for BIT files is .bit.

See Also

 "Generating SVF Files"


Download Cables

There are two cables available for use with the JTAG Programmer. The first is an RS232 serial cable known as the XChecker Cable. The second is the Parallel Download Cable which can be connected to a PC's parallel printer port.

There are a few advantages to be considered in selecting a cable:

•	The XChecker Cable connects to the serial port of both workstations and PCs.

•	The Parallel Cable has better drive capability. The Parallel Cable can drive up to 10 Xilinx devices in a boundary-scan chain, and the XChecker Cable can drive up to 4 Xilinx devices.

•	The Parallel Cable is at least 5 times faster.

See Also

 "XChecker Hardware (Serial)"

 "Parallel Cable"


XChecker Hardware (Serial)

The XChecker hardware consists of a cable assembly with internal logic, a test fixture, and a set of headers to connect the cable to your target system.

Using the XChecker hardware requires either a standard DB-9 or DB-25 RS-232 serial port. If you have a different serial port connection, you need to provide the appropriate adapter. The JTAG Programmer Guide on the documentation CD shows the XChecker cable hardware and accessories. Access this document from the documentation CD.

The XChecker cable can be used with a single Xilinx device or several devices connected in a boundary-scan chain to download and readback configuration and boundary-scan data.

See Also

 "Connecting for System Operation (Serial)"

 "Baud Rates (XChecker)"

 "Connecting the XChecker Cable"

 "Flying Lead Connectors"


Connecting for System Operation (Serial)

Connections between the cable assembly and the target system use only 6 of the sixteen leads. For connection to JTAG boundary-scan systems you need only ensure that the VCC, GND, TDI, TCK, TMS and RD (TDO) pins are connected.

Once installed properly, the connectors provide power to the cable, allow download and readback of configuration data, and provide for logic probe of device pins.x

Name	Function	Connections
VCC	Power - Supplies VCC (5 V, 100 mA, typically) to the cable.	To target system VCC
GND	Ground - Supplies ground reference to the cable.	To target system ground
RD (TDO)	Read Data - Read back data from the target system is read at this pin.	Connect to system TDO pin.
TDI	Test Data In - this signal is used to transmit serial test instructions and data.	Connect to system TDI pin.
TCK	Test Clock - this clock drives the test logic for all devices on boundary-scan chain.	Connect to system TCK pin.
TMS	Test Mode Select - this signal is decoded by the TAP controller to control test operations.	Connect to system TMS pin.
CLKI	Not used.	Unconnected.
CLKO	Not used.	Unconnected.
CCLK	Not used.	Unconnected.
D/P	Not used.	Unconnected.
DIN	Not used.	Unconnected.
PROG	Not used.	Unconnected.
INIT	Not used.	Unconnected.
RST	Not used.	Unconnected.
RT	Not used.	Unconnected.
TRIG	Not used.	Unconnected.
See Also

 "Flying Lead Connectors"


Baud Rates (XChecker)

The XChecker Cable supports Baud rates as shown:

Platform	9600	19200	38400
IBM PC	X	X	X
SUN	X	X	X
HP 700	X	X	X


Connecting the XChecker Cable

There are two simple steps for connecting the cable:

1.	Connect the cable to your host system serial port.

2.	Connect the cable to your target system.

Connecting the XChecker Cable

The XChecker cable connects to your system RS-232 serial port. You may need a DB-9/DB-25 adapter, which accommodates most serial ports, so that you can connect the XChecker cable to your host system.

The JTAG Programmer software will automatically identify the XChecker cable when correctly connected to your computer. If you choose to, you may also select this connection manually. To set up a serial port manually:

Output → Cable Setup

Select XChecker, then click on OK. If you are using the XChecker Cable you may also select a BAUD rate. See Valid Baud Rates	 .

Connection to Your Target System

You need appropriate pins on the target system for connecting the target system board to the header connection on the cable. These connectors must be standard 0.025−inch square male pins that have dedicated traces to the target system control pins. You connect to these pins with the flying lead connectors.

Note:  The XChecker cable draws its power from the target system through VCC and GND. Therefore, power to XChecker, as well as to the target system, must be stable. Do not connect any signals before connecting VCC and ground.

Note:  If your system`s power is turned off before or during JTAG Programmer operations, the cable will not operate. Your system's power should be on during JTAG Programming operations.

Note:  If the power has been momentarily interrupted, go to Output → Cable Reset to reinitialize the XChecker cable. If you do not want to operate at maximum Baud rate, go to the Cable Communication Setup dialog box (Output → Cable Setup...) and set a lower rate.

See Also

 "Flying Lead Connectors"


Parallel Cable

The Parallel Download Cable consists of a cable assembly containing logic to protect your PC`s parallel port and a set of headers to connect to your target system.

Using the Parallel Download Cable requires a PC equipped with an AT compatible parallel port interface with a DB25 standard printer connector.

The cable assembly contains logic designed to electrically isolate the target system from the parallel port of your PC host system.

The parallel download cable can be used with a single CPLD or several connected in a boundary-scan chain to download and readback configuration and boundary-scan data.

The transmission speed of the Parallel Download Cable is determined solely by the speed at which the host PC can transmit data through its parallel port interface.

See Also

 "Connecting for System Operation"

 "Configuring the Parallel Download Cable"

 "Flying Lead Connectors"

 "JTAG Parallel Download Cable Schematic"


Connecting for System Operation

Connections between the cable assembly and the target system use only 6 of the sixteen leads. For connection to JTAG boundary-scan systems you need only ensure that the VCC, GND, TDI, TCK, TMS and RD (TDO) pins are connected.

For a schematic diagram of the Parallel Download Cable, see the JTAG Programmer Guide in the online documentation found on the documentation CD and accessed from the Dynatext viewer.

See Also

 "Configuring the Parallel Download Cable"


Configuring the Parallel Download Cable

On PCs you can connect the parallel cable to your system's parallel printer port. The JTAG Programmer software will automatically identify the cable when correctly connected to your PC. If you choose to, you may also select this connection manually. To set up a parallel port manually:

Output → Cable Setup

Select the Parallel box and match to the port you are using, then click on OK.

See Also

 "Power Up Sequencing"

 "Selecting a Port for the Cable"


Flying Lead Connectors

The flying lead connector has a 9-pin (6 signals, 3 keys) header connector that fits onto the cable's JTAG header. The pin order is listed below. These header connectors are keyed to assure proper orientation to the cable assembly.

The flying lead connector has six individual female connectors on one end that fit onto standard 0.025″ square male pins. Each lead is labeled to identify the proper pin connection.

When you layout the printed circuit board for use with JTAG in-system programming and testing, a few adjustments will make the process of connecting and downloading easier.

•	Provide pins on your printed circuit board for VCC, GND, TCK, TDO, TDI and TMS.

•	These pins must be standard 0.025" square male pins that have dedicated traces to the target system control pins. You connect to these pins with the flying lead connector.

•	Place pins on board so that flying leads can reach them. The length of our flying leads is six inches. While pins may be a couple inches apart, do not have any two JTAG pins more than six inches apart.

•	Keep header pins on your board a minimum of 0.10" apart.

Name	Function	Connections
VCC	Power - Supplies VCC (5 V, 10 mA, typically) to the cable.	To target system VCC
GND	Ground - Supplies ground reference to the cable.	To target system ground
TCK	Test Clock - this clock drives the test logic for all devices on boundary-scan chain.	Connect to system TCK pin.
TDO	Read Data - Read back data from the target system is read at this pin.	Connect to system TDO pin.
TDI	Test Data In - this signal is used to transmit serial test instructions and data.	Connect to system TDI pin.
TMS	Test Mode Select - this signal is decoded by the TAP controller to control test operations.	Connect to system TMS pin.


Power Up Sequencing

1.	Connect your cable to your host computer.

2.	Turn the power to your target system off, if possible.

3.	The power for the drivers is derived from the target system. Connect the cable's GND wire to the corresponding signal on the target board. Next, connect VCC to the corresponding signal on the target board.

Note:  Download cables will not operate if the target system`s power is turned off before or during JTAG Programmer operations. Make certain that this power connection is on and stable. Your system's power should be on during JTAG Programmer operations.

Note:  JTAG Programmer will always initiate operations using a JTAG TAP controlled reset sequence. This performs the exact same operation as the assertion of the TRST pin; it initializes all devices` JTAG state machines and internal registers.

4.	Next connect the JTAG TAP inputs. Connect TCK, TDI, TMS and TDO to the target board. TRST is not supported by the Xilinx JTAG Download Cables. If any of your JTAG parts have a TRST pin, it should be connected to VCC.

5.	Power up the target system.

Warning:  Cable protection ensures that the parallel port cannot be damaged through normal cable operation. For increased safety, please check that the power to the system controller is on before the target system is powered up.

See Also

 "Troubleshooting Guide"


Selecting a Port for the Cable

You may select a serial or parallel port for your cable from the JTAG Programmer Interface. To set up a port:

Output → Cable Setup

The Cable Communication Setup dialog box will appear.

Select the cable you are using and match to the port you are using, then click on OK. If you are using the XChecker Cable you may also select a BAUD rate. See  "Baud Rates (XChecker)"

Alternatively, you may use the Output → Cable Auto Connect to allow the software to automatically identify and connect to whichever download cable is installed.

Note:  Upon selecting any device operation, the JTAG Programmer will automatically connect to whichever cable is installed and powered up.


Creating New Chain Descriptions

The device chain U1, U2, ... Un is a serial chain where U1 is the first device TDI enters and Un is the last device. Un must deliver the TDO (labelled RD on the XChecker cable) signal back to the cable. TMS and TCK signals enter all devices in parallel.

The chain description must contain all devices in the order that they appear in the JTAG programming chain.

Alternatively, you can use the Initialize Chain operation to automatically identify the devices in the system boundary-scan chain. You must then associate JEDEC files for CPLD devices, Bit files for Xilinx FPGA devices, and BSDL files for all other devices by using the device properties dialog box.

See Also

 "Configuring a Device In-System"

 "Programming Xilinx CPLD and FPGA Devices"

 "Selecting Operations"

 "Modifying a Chain"

 "Saving the Chain Description"


Configuring a Device In-System

If you have created programming files (<filename>.jed or <filename>.bit) and are ready to download them to Xilinx CPLD or FPGA devices in-system through the JTAG chain, proceed as follows:

1.	Make sure the cable is attached properly and the target board is turned on.

2.	Invoke the JTAG Programmer Download Software menu by double-clicking the JTAG Programmer Download Software icon.

The JTAG Programmer will appear.

3.	Add a device for each part in your boundary-scan chain.

Edit → Add Device

Or, if you have the cable set up and connected to a boundary-scan chain, you can use the automatic device identification feature of the JTAG Programmer to display the entire chain. To do this:

File → Initialize Chain

The programmer goes out and finds all the parts in the chain, identifies them, and displays them in the JTAG Programmer. If the programmer finds a device it can't identify, it displays the device as an unknown part.

4.	You need to specify a JEDEC file for each Xilinx CPLD device in the boundary-scan chain, a BIT file for each Xilinx FPGA, and a BSDL file for all other devices in the boundary-scan chain. Highlight the first device in the chain by clicking once on it and then select the JEDEC. BIT or BSDL file corresponding to the device.

Edit → Properties

Alternatively, you may double-click on the device icon.

The Device Properties dialog box appears

Type in the path name or click once on the browse key and find the appropriate file to assign to the highlighted part. Select JEDEC files for each Xilinx CPLD device in the chain, BIT files for each Xilinx FPGA, and BSDL files for the remaining devices. Repeat for each device in the chain.

See Also

 "Selecting Operations"

 "Modifying a Chain"

 "Saving the Chain Description"

 "Data Security Selection"


Programming Xilinx CPLD and FPGA Devices

There are two preferences available that you may want to select before initiating a session. They are Concurrent Mode and Use HIGHZ instead of BYPASS. These options are selected as follows:

File → Preferences

The Preferences dialog box will appear.

Concurrent Mode

The JTAG Programmer normally uses sequential programming for CPLD devices. It selects a device to program and sets all other devices in the boundary-scan chain into BYPASS mode. Concurrent Mode erases programs and verifies selected CPLD devices in the chain without placing these parts in BYPASS mode. This has the advantage of saving time by executing operations simultaneously.

For example, it takes few seconds to completely erase all the sectors of a device. If you have several devices in a chain the erase times can add up. In concurrent mode the erasures can take place simultaneously, saving time.

Note:  Since this mode offers no advantage for FPGA devices, it is ignored for FPGAs.

Use HIGHZ instead of BYPASS

The JTAG Programmer usually places parts in BYPASS mode when other devices in the boundary-scan chain are being programmed. This option places any Xilinx device that supports it in high impedance mode instead. If you suspect that noise is degrading the integrity of ISP operations, use this mode to reduce the signal activity level in the system.

Note:  If you decide to use HIGHZ instead of BYPASS you must be certain that your design can tolerate device pins floating. If these pins connect to memory enable pins, for instance, their floating values may inadvertently cause the devices to turn on, potentially damaging their drivers or parts downstream from them.

Selecting Parts for Programming

You can select all Xilinx devices at once with Edit   Select All, or highlight each device individually, then:

Operations → Program

The program options box appears. Select the desired programming options, then click OK.

When the programming operation is complete, the programming status of each Xilinx device is reported as shown:

See Also

 "Configuring a Device In-System"

 "Selecting Operations"

 "Modifying a Chain"

 "Saving the Chain Description"

 "Data Security Selection"


FPGA Device Considerations


FPGA Device Considerations

JTAG Programmer supports the configuration of Xilinx FPGA devices through the boundary-scan test access port (TAP). In order to enable boundary-scan-based configuration capabilities for FPGA devices, you must design your systems and prepare your configuration bitstreams in the following manner.

 Bitstream Considerations

 JTAG Programmer only accepts FPGA configuration files in the binary bitstream format (.bit). It does not allow configuration using the ASCII raw bits (.rbt) format.

Express mode bitstreams cannot be used to configure devices via boundary-scan.

Make certain that the boundary-scan (BSCAN) symbol has been included in your design. If it has not then the bitstream will also not be usable for boundary-scan based configuration. Standard examples for instantiating the BSCAN symbol in FPGAs are included in Appendix F of the JTAG Programmer Guide, located in the Dynatext collection, or at our website at www.xilinx.com.

 Keep your device bitstream files separate for each device in the boundary-scan chain. JTAG Programmer requires you to assign a single bit file to each device. It cannot manipulate composite bit files.

Device Setup

Xilinx recommends that all the mode pins of the devices be tied low before starting the configuration. This is recommended for all XC4000, XC5000 and Spartan device families. For Virtex, JTAG mode should be selected (mode pins set to 101)

 In order to enable the boundary-scan circuitry in the device, you must install a pull down resistor on the INIT pin. The value of the pull down should be selected so as to draw the INIT pin to approximately 0.5V. Typically a pull down of approximately 1KOhm should accomplish this.

 Verifying Device Configuration

The XC4000 (not the XLA and XV), XC5000 and Spartan (not the SpartanXL) devices freeze if data errors occur during boundary-scan configuration. The only method for unlocking the frozen device is to reset the power to the device or pulse the PROGRAM pin low. (This latter method would have to be accomplished manually since the download cables (when being used for boundary-scan operations), do not have control over the PROGRAM pin. Although this situation is rare, it is possible to design your system so as to detect if that condition has occurred. The JTAG Programmer software allows you to check for this in three ways:

1.	Assume successful verification - since it is a low probability event, simply configure the device and run. The drawback is that the failure of the device is then only detected at run-time.

2.	Tie a free pin on the device to ground - after configuring, the software will perform an EXTEST instruction to read the device pin value. If the device has locked up, the pin value will not be read correctly.

Device Behavior Notes

Any verify operation executed immediately after configuration without boundary-scan functionality enabledwill fail because the test access port no longer exists. Always remember to instantiate the BSCAN symbol for reliable operation of your devices.

The implementation of boundary-scan based configuration of FPGAs precludes the use of concurrent ISP. For this reason, the concurrent mode preference is disabled (or ignored) when FPGAs are selected to be operated upon.


Design Rules
Design Rules for Boundary-Scan and ISP Systems

The boundary-scan standard requires pull-up resistance to be supplied internally to the TDI and TMS pins by the chips, but no particular value is required. This allows vendors supply whatever they choose and still remain in full compliance. Because of this, very long boundary-scan chains, or chains using parts from multiple vendors, may present significant loading to the ISP drive cable. In these cases:

1.	Use the latest Xilinx download cables (parallel cables with serial numbers greater than 5000, or any X-Checker cable).

2.	Consider including buffers on TMS or TCK signals interleaved at various points on your JTAG circuitry to account for unknown device impedance.

Some users have noted that their designs appear to experience erase time or programming time extension as the design progresses, particularly for long chains. This is probably due to switching noise.

3.	Put the rest of the JTAG chain into HIGHZ mode by selecting the HIGHZ preference on JTAG Programmer when programming a troublesome part.

This will limit the number of additional signals presented to the system and the troublesome part.

4.	If free running clocks are delivered into boundary-scan devices, it may be necessary to disconnect or disable their entry into these devices during ISP or boundary-scan operations.

Charge pumps, the heart of the XC9500/XL/XV ISP circuitry, require a modest amount of care. The voltages to which the pumps must rise are directly derived from the external voltage supplied to the VCCINT pins on the XC9500/XL/XV parts. Because these elevated voltages must be within their prescribed values to properly program the CPLD, it is vital that they be provided with very clean (noise free) voltage within the correct range. This suggests the first two key rules:

5.	Make sure VCC is within the rated value: 5V +/- 5%.

6.	Provide both 0.1 and 0.01 uF capacitors at every VCC point of the chip, and attached directly to the nearest ground.

7.	Match the cable VCC to the VCCIO of the target devices (when using an XChecker cable below 5V, the 3.3V adapter is required).


Selecting Operations

There are two ways to set up the chain for JTAG Programmer operations. The first is to highlight a part and select an operation for it using the Operations menu. You select an operation from the menu, then highlight the next part and select an operation for it, or you may highlight all parts and select an operation for all parts.

The other way is to use the Chain Operations dialog box. This presents you with a "spreadsheet" approach to boundary-scan chain. This method allows you select and execute operations for all the parts in the chain, all from the same dialog box. To access this dialog box:

Operations → Chain Operations...

The dialog box appears. In the Operations column you may change the operation of any part by clicking once on the current device to highlight it, then clicking once on the down arrow adjacent to Selected Device Operation. This will produce a pull-down menu showing the operations you can set for that part.

Note:  Bypass is the only supported mode of Operation for non-FastFLASH parts. These parts will appear under Device Type. Note that Bypass is selected as the default Operation of each foreign part.

Select the Execute button. Download will begin.

In either operation mode a pop-up menu appears and delivers processing messages. When processing has completed, a message log is available to examine the results of the execution.

See Also

 "Programming and Verification Overview"

 "User Feedback"

 "Creating New Chain Descriptions"

 "Configuring a Device In-System"

 "Programming Xilinx CPLD and FPGA Devices"


Modifying a Chain

The Edit menu provides easy means for inserting and deleting parts from a chain, as well as the means to assign a new JEDEC file to a part.

Adding a Device

To insert a device into the chain, use the Add Device command. First make sure that the prompt is at the location in the chain where you want to insert the device. If it is not, use either the mouse or the arrow keys to move it. Then insert the device as follows:

Edit → Add Device

Changing a Part

To change the jedec file associated with a device in the chain, highlight the device and:

Edit → Properties

Use the browse key to select another jedec file or simply enter the path and filename of the file. The program will associate the new file with the device.

Note:  Each jedec assigns a device type to the device in the chain. If the jedec file was not created for the actual device you have on your board, an error will result when you attempt to program the device.

Deleting a Part

To delete an entry in the device chain, use the Cut command. All devices move up one entry in the chain.

Edit → Cut

Selecting the Entire Chain

To select the entire chain for an operation, use

Edit → Select All

To unselect the chain:

Edit → Unselect All

See Also

 "Saving the Chain Description"


Saving the Chain Description

To save a JTAG Programmer chain description for later use, create a Chain Description File (.cdf) using:

File → Save

If the chain has not been previously saved, the Save As dialog box will appear. This screen will allow you to select a directory and path to place the file in. You can also name the file, but you should retain the .cdf file extension. If you wish to save your file under another name than already selected, use:

File → Save As...

To name your file, use the mouse to highlight Untitled or the old file name on the File Name line, then type in the name you want and click once on OK.


Debugging a Chain

The debugger provides you with a method to apply boundary-scan test access port stimulus. This feature allows you to set TDI and TMS, then pulse TCK a specified number times. You can monitor TDO, TDI and TMS using an oscilloscope or logic probe to see if the boundary-scan chain is operating correctly. The debugger also displays the current TAP state and allows you to reset the chain to Run Test Idle.

To access the debugger:

File → Debug Chain

The Boundary-Scan Chain Debug dialog box appears as shown in the figure.

The features of this dialog box operate as follows:

•	The first selection box allows you to set a logic state for TDI. This state will not be set until you click on the Apply button.

•	The second selection box allows you to set a logic state for TMS. This state will not be set until you click on the Apply button.

•	The third selection box allows you to set a number of pulses to apply to TCK. These pulses will not be sent until you click on the Apply button. If you want to see the pulses again, click the Apply button as often as you want.

•	The TAP State window displays the current state of the controller.

•	The Return to RTI (Run Test Idle) button executes a Test Logic Reset, then returns to Run Test Idle.

See Also

 "Troubleshooting Guide"


Data Security Selection

Any Xilinx XC9500/XL/XV device selected for programming can be secured with the Write Protect or Read Protect or both.

When enabled, Read Protect disables reading the programmed contents of a device (the Device ID and usercode/signature and boundary scan register remain readable).

Write Protect allows only the reading of the programmed data. The device contents cannot be altered or re-programmed.

When both Read Protect and Write Protect are enabled, the device can be neither read nor re-programmed.

To enable either security function simply place a check in the corresponding box when programming the device.

Data security operations can be overridden only by erasing the device. For Read Protection override, you simply erase the part. For Write Protection override, you must select the override write protect option from the Erase Options dialog box.

Note:  Security options do not affect the accessibility of the bypass or boundary-scan register.


Generating SVF Files

Serial Vector Format (SVF) files are used when programming Xilinx devices on automatic test equipment (ATE). The JTAG Programmer allows you to create .svf files for use with ATE systems. To do this you need to create a new SVF file:

Output → Create SVF File...

The Create a New SVF File dialog box will appear.

Select a name and a directory to create the new file in, then click OK. To append your vectors to an existing SVF file, use:

Output → Append to SVF File...

The Append to an Existing SVF File dialog box will appear.

Select a file to append to and click OK.

Now select device operations as you normally would.

Note:  Program, Verify, Erase, Functional Test, Get Device ID and Get Signature/Usercode are allowed operations in SVF mode.

Xilinx provides software on the Xilinx Website that converts SVF files into ATE vectors. Visit our site at www.xilinx.com for more information.

See Also

 "Substituting with Later Version CPLD Devices"


Substituting with Later Version CPLD Devices

If you generated SVF files for XC95108 or XC95216 Version 0 devices, the files will work without modification on Version 1 or Version 2 devices. If you wish, however, to take advantage of improved ISP capabilities available on Version 1or Version 2 silicon devices, and you are certain that you have Version 1 or Version 2 devices in your boundary-scan chain, then you can generate Version 1 or Version 2 specific SVF files using the following techniques:

Note:  In this example, Version 1 is illustrated. Version 2 specific flow is identical except that v2 should be used in place of v1.

Using the Batch Tool (jtagprog)

Invoke the tool to generate SVF files:

jtagprog -svf

When specifying the part_type in the part command identify Version 1 silicon by appending "_v1" to the part name. For example, to specify a chain of Version 1 XC95216s and XC95108s:

part xc95216_v1:design216a xc95108_v1:design108 xc95216_v1:design216b

Next, specify operations as usual to generate the required SVF files.

Using the JTAG Programmer

In your $XILINX/data directory you will notice BSDL files with the following names:

xc95108.bsd

xc95108_v1.bsd

xc95216.bsd

xc95216_v1.bsd

The BSDL files with the "_v1" in their names describe the Version 1 silicon. To get the software to use Version 1 BSDL files for all devices, you must "trick" the application by renaming files as follows:

1.	Rename xc95108.bsd to xc95108_v0.bsd

2.	Rename xc95216.bsd to xc95216_v0.bsd

3.	Rename xc95108_v1.bsd to xc95108.bsd

4.	Rename xc95216_v1.bsd to xc95216.bsd

Invoke the JTAG Programmer and set it to generate SVF files as described earlier in this section. When you use the JTAG Programmer, it will default to using the xc95216.bsd and xc95108.bsd files to describe the parts. This will allow access to all Version 1 features.

When you are done programming, remember to change the file names back so that the software will work correctly in non-SVF modes:

1.	Rename xc95108.bsd to xc95108_v1.bsd

2.	Rename xc95216.bsd to xc95216_v1.bsd

3.	Rename xc95108_v0.bsd to xc95108.bsd

4.	Rename xc95216_v0.bsd to xc95216.bsd


What is IEEE 1149.1?

Design complexity, difficulty of loaded board testing, and the limited pin access of surface mount technology led industry leaders to seek accord on a standard to support the solution of these problems.

JTAG Boundary Scan, formally known as IEEE Standard 1149.1, is primarily a testing standard created to alleviate the growing cost of designing and producing digital systems. The primary benefit of the standard is the ability to transform extremely difficult printed circuit board testing problems (that could only be attacked with ad-hoc testing methods) into well-structured problems that software can handle easily and swiftly.

The standard defines a hardware architecture and the mechanisms for its use to solve the aforementioned problems.

What can it be used for?

Although primarily a testing standard for on-chip circuitry, the proliferation of the standard has opened the door to a wide variety of applications. The standard itself defines instructions that can be used to perform functional and interconnect tests as well as built-in self test procedures.

Vendor-specific extensions to the standard have been developed to allow execution of maintenance and diagnostic applications as well as programming algorithms for reconfigurable parts. It is the latter that have been implemented (in addition to all the mandatory operations of the standard and some optional ones) in the FastFLASH family.

How does it work?

The top level schematic of the test logic defined by IEEE Std 1149.1 includes three key blocks:

The TAP Controller

This responds to the control sequences supplied through the test access port (TAP) and generates the clock and control signals required for correct operation of the other circuit blocks.

The Instruction Register

This shift register-based circuit is serially loaded with the instruction that selects an operation to be performed.

The Data Registers

These are a bank of shift register based circuits. The stimuli required by an operation are serially loaded into the data registers selected by the current instruction. Following execution of the operation, results can be shifted out for examination.

The JTAG Test Access Port (TAP) contains four pins that drive the circuit blocks and control the operations specified. The TAP facilitates the serial loading and unloading of instructions and data. The four pins of the TAP are: TMS, TCK, TDI and TDO. The function of each TAP pin is as follows:

TCK -	 this pin is the JTAG test clock. It sequences the TAP controller as well as all of the JTAG registers provided in the XC95108.

TMS -	 this pin is the mode input signal to the TAP Controller. The TAP controller is a 16-state FSM that provides the control logic for JTAG. The state of TMS at the rising edge of TCK determines the sequence of states for the TAP controller. TMS has an internal pull-up resistor on it to provide a logic 1 to the system if the pin is not driven.

TDI -	this pin is the serial data input to all JTAG instruction and data registers. The state of the TAP controller as well as the particular instruction held in the instruction register determines which register is fed by TDI for a specific operation. TDI has an internal pull-up resistor on it to provide a logic 1 to the system if the pin is not driven. TDI is sampled into the JTAG registers on the rising edge of TCK.

TDO - 	this pin is the serial data output for all JTAG instruction and data registers. The state of the TAP controller as well as the particular instruction held in the instruction register determines which register feeds TDO for a specific operation. Only one register (instruction or data) is allowed to be the active connection between TDI and TDO for any given operation. TDO changes state on the falling edge of TCK and is only active during the shifting of data through the device. This pin is three-stated at all other times

See Also

 "JTAG TAP Controller States"


JTAG TAP Controller States

The JTAG TAP Controller is a 16-state finite state machine, that controls the scanning of data into the various registers of the JTAG architecture. The state of the TMS pin at the rising edge of TCK is responsible for determining the sequence of state transitions. There are two state transition paths for scanning the signal at TDI into the device, one for shifting in an instruction to the instruction register and one for shifting data into the active data register as determined by the current instruction.

Test-Logic-Reset. This state is entered on power-up of the device whenever at least five clocks of TCK occur with TMS held high. Entry into this state resets all JTAG logic to a state such that it will not interfere with the normal component logic, and causes the IDCODE instruction to be forced into the instruction register.

Run-Test-Idle. This state allows certain operations to occur depending on the current instruction. For the XC9500 family, this state causes generation of the program, verify and erase pulses when the associated in-system programming (ISP) instruction is active.

Select-DR-Scan. This is a temporary state entered prior to performing a scan operation on a data register or in passing to the Select-IR-Scan state.

Select-IR-Scan. This is a temporary state entered prior to performing a scan operation on the instruction register or in returning to the Test-Logic-Reset state.

Capture-DR. This state allows data to be loaded from parallel inputs into the data register selected by the current instruction on the rising edge of TCK. If the selected data register does not have parallel inputs, the register retains its state.

Shift-DR. This state shifts the data, in the currently selected register, towards TDO by one stage on each rising edge of TCK after entering this state.

Exit1-DR. This is a temporary state that allows the option of passing on to the Pause-DR state or transitioning directly to the Update-DR state.

Pause-DR. This is a wait state that allows shifting of data to be temporarily halted.

Exit2-DR. This is a temporary state that allows the option of passing on to the Update-DR state or returning to the Shift-DR state to continue shifting in data.

Update-DR. This state causes the data contained in the currently selected data register to be loaded into a latched parallel output (for registers that have such a latch) on the falling edge of TCK after entering this state. The parallel latch prevents changes at the parallel output of these registers from occurring during the shifting process.

Capture-IR. This state allows data to be loaded from parallel inputs into the instruction register on the rising edge of TCK. The least two significant bits of the parallel inputs must have the value 01 as defined by IEEE Std. 1149.1, and the remaining 6 bits are either hard-coded or used for monitoring of the security and data protect bits.

Shift-IR. This state shifts the values in the instruction register towards TDO by one stage on each rising edge of TCK after entering this state.

Exit1-IR. This is a temporary state that allows the option of passing on to the Pause-IR state or transitioning directly to the Update-IR state.

Pause-IR. This is a wait state that allows shifting of the instruction to be temporarily halted.

Exit2-IR. This is a temporary state that allows the option of passing on to the Update-IR state or returning to the Shift-IR state to continue shifting in data.

Update-IR. This state causes the values contained in the instruction register to be loaded into a latched parallel output on the falling edge of TCK after entering this state. The parallel latch prevents changes at the parallel output of the instruction register from occurring during the shifting process.

See Also

 "JTAG Instructions Supported by Xilinx Devices"


JTAG Instructions Supported by Xilinx Devices

JTAG Programmer software uses sequences of these JTAG instructions to perform programming and verification operations selected by the user. However, execution of individual JTAG instructions is not supported by this software.

Mandatory Boundary Scan Instructions (All Xilinx Devices)

BYPASS. The BYPASS instruction allows rapid movement of data to and from other components on a board that are required to perform test operations.

SAMPLE/PRELOAD. The SAMPLE/PRELOAD instruction allows a snapshot of the normal operation of a components to be taken and examined. It also allows data values to be loaded onto the latched parallel outputs of the boundary scan shift register prior to the selection of other boundary-scan test instructions.

EXTEST. The EXTEST instruction allows testing of off-chip circuitry and board level interconnections.

Optional Boundary Scan Instructions

INTEST. The INTEST instruction allows testing of the on-chip system logic while the components are already on the board (all Xilinx devices)

HIGHZ. The HIGHZ instruction forces all drivers into high impedance states (XC9500/XL/XV, Virtex).

IDCODE. The IDCODE instruction allows blind interrogation of the components assembled onto a printed circuit board to determine what components exist in a product (XC9500/XL/XV, Virtex, XC4000XLA/XV, SpartanXL).

USERCODE. The USERCODE instruction allows a user-programmable identification code to be shifted out for examination. This allows the programmed function of the component to be determined (XC9500/XL/XV, Virtex).

FastFLASH Reconfiguration Instructions (XC9500/XL/XV)

ISPEN. The ISPEN instruction activates the FastFLASH part for in-system programming.

FPGM. The FPGM instruction is used to program the fuse locations at a specified address.

FERASE. The FERASE instruction is used to perform an erase of a block of fuse locations.

FVFY. The FVFY instruction is used to read the programming of the fuse locations at a specified address.

ISPEX. The ISPEX instruction loads the programmed values into the device memory. It then activates the device to operate according to the programmed values.

FPGMI. The FPGMI instruction is used to program fuse locations sequentially from a preset starting address.

FVFYI. The FVFYI instruction is used to read the programming of fuse locations sequentially for a preset starting address.

FBULK. The FBULK instruction is used to perform an erase of either all function blocks or all Fastconnect blocks of a device.


JTAG Parallel Download Cable Schematic

This schematic is included in case you want to build your own download cables. This is our current version of the Parallel Download Cable. The schematic is located in the JTAG Programmer Guide found on the online documentation CD and accessed from the Dynatext viewer. If you want to build a parallel cable, this is the recommended schematic.

Note:  You must use recommended lengths for parallel cables. Xilinx cables are typically six feet (about two meters) in length.


Troubleshooting Guide

The issues are likely to fall into five groups; communication, improper connections, and improper or unstable VCC, Boundary Scan Chain Errors, and system noise.

 "Communication"

 "Improper Connections"

 "Improper or Unstable Vcc"

 "Boundary Scan Chain Errors"

 "System Noise"

See Also

 "Debugging a Chain"


Communication

Observing the following guidelines should minimize the communication difficulties that can occur between the cable hardware and the target system.

Do not attach extension cables to the target system side of the cable; this can compromise configuration data integrity and cause checksum errors.

Attach the cable configuration leads firmly to the target system.

After connecting the target system, specify the chain configuration using the part command. Then use the "partinfo -id part_name" command to read the IDCODE from each part in the system. This will verify the integrity of the boundary-scan chain. If you are using the Graphical User Interface:

Operations → Get Device ID

Use the verify feature to assure integrity of the configuration data. You can do this from the command line with the -v option or in the interactive mode by specifying the verify command.

When using the JTAG Programmer software with the cable on a PC to download, the process may stop with data communications errors. This is caused by serial port communication inefficiencies in the Windows environment. To set your PC to better handle serial communications at 38400 baud, add (or modify) the following lines to the 386Enh section of your SYSTEM.INI file. This file is located in the Windows directory of your system.

COM1Buffer=32768

COM2Buffer=32768

COMBoostTime=10240


Improper Connections

Always make sure that cable leads are connected properly.

Note:  Connecting the cable leads to the wrong signal will cause permanent damage to cable internal hardware. You must connect VCC to +5 V and GND to ground.

For workstations, you must have read and write permissions to the port to which you connect the cable. JTAG Programmer might issue a message stating that the cable is not connected to port ttyx. When you see this message, follow the check list below:

•	The board must have the power on, since the cable uses power from the board.

•	Check the device driver using the following command string:

ls -l /dev/ttya /dev/ttyb

The result should be the following:

crw-rw-rw-  1 root	12,0 month date time /dev/ttya

crw-rw-rw-  1 root	12,1 month date time /dev/ttyb

•	Reconnect the cable to another valid port.

•	Read the /etc/ttytab file. There should be two lines, as follows:

ttya	``/usr/etc/getty std.9600''  unknown   off local secure

ttyb	``/usr/etc/getty std.9600''  unknown   off local secure

If you use a port to connect a modem or a remote login, you cannot use that port. The port must be on. Consult your System Administrator if the information the /etc/ttytab file is different than what is listed in the aforementioned list.


Improper or Unstable Vcc

Never connect the control signals to the cable before Vcc and ground. Xilinx recommends the following sequence:

1.	Turn off power to the target system.

2.	Connect Vcc ground, and then the signal leads.

3.	Turn on power to the target system.

Warning:  The XChecker Cable has an internal FPGA. As with any CMOS device, the input/output pins of the internal FPGA should always be at a lower or equal potential than the rail voltage to avoid internal damage.

Make sure Vcc rises to a stable level within 10ms. Stable Vcc should be between 4.75V and 5.25V for 5V devices, and 3.0V and 3.5V for 3.3V devices.

In the event of power glitches, reset the cable by selecting:

Output   Cable Reset

Make certain to match the cable voltage to the device Vcc I/Os.

You will need to use a 3V adapter on XChecker to run at 3V.


Boundary Scan Chain Errors

If you experience a consistent error that identifies a break in your boundary-scan chain but are unable to identify such a discontinuity then execute the following steps:

1.	Create a command file to be used with the batch version of the JTAG Programmer (jtagprog). In this batch file specify your boundary-scan chain configuration using the part command and about 50 idcode queries as follows:

part xc9572:design72 xc95108:design108

partinfo -id design108

partinfo -id design108

partinfo -id design108

.

.

.

partinfo -id design108

quit

2.	Save the file as test.cmd and then invoke the tool as follows:

jtagprog -batch test

3.	The tool will execute the device id command 50 times before quitting. While this is going on use the oscilloscope to probe the pins of the boundary scan test access port (TAP) at the system entry point and at each individual part.

The boundary scan integrity check sequences the TAP through a TRST sequence (TMS set to 1, TCK pulsed 5 times) and then transitions all devices to the RunTest/Idle state (TMS set to 0, TCK pulsed once). Then, all parts are run through a CAPTURE -IR sequence while TDI is set to 1 (1s will be shifted in). If you look in the device BSDL files you will see the expected capture sequence defined in the "instruction capture" field. For all xc9500 parts this sequence is a "1" followed by seven zeros. You should therefore see the "1" on TDO after the falling edge of the 4th TCK pulse after the TRST sequence. On the next TCK pulse TDO should return to zero.

The CAPTURE -IR sequence consists of the following (starting from RunTest/Idle):

1.	TMS set to 1; TCK pulsed twice.

2.	TMS set to 0; TCK pulsed twice.

3.	TCK pulsed (number of bits in instruction register -1) times.

4.	TMS set to 1; TCK pulsed twice.

5.	TMS set to 0; TCK pulsed once.

Check for the following:

•	The expected number of TCK pulses occur.

•	The same TMS sequence occurs for each part.

•	The TDO is not shorted or floating between parts, or floating at the system interconnect point.

•	Make certain that all 4 TAP signals are getting into each part (Note that both TDI and TMS have internal pull-ups on them which could keep the device in TRST mode if TMS is not properly connected).

You may also use the Debug Chain dialog and a logic probe or oscilloscope to transition the TAP state machine directly and observe results.


System Noise

You can check for system noise by running the IDCODE instruction repeatedly. The IDCODE should read correctly 100% of the time. If by test you find that the instruction is working less than 100% of the time, you may be experiencing system noise.

To remedy a problem with system noise, select Use HIGHZ instead of BYPASS from the Preferences dialog box. This places devices into tri-state mode and reduces susceptibility to system noise. To find this box use:

File → Preferences

The Preferences dialog box will appear. Place a check in the box adjacent to Use HIGHZ instead of BYPASS.


Using the Command Line Interface

You can perform JTAG operations using jtagprog in a workstation or PC environment.  You can use jtagprog to download, read back, verify design configuration data for any device, and to probe internal logic states of an CPLD design.

JTAG Programmer batch software support the following capabilities.

•	JTAG Programmer allows you to download a design to the CPLD on the target system.

•	JTAG Programmer can verify CPLD configuration by comparing it to the original JEDEC programming file after configuring an CPLD.

•	You can program multiple CPLDs connected on a boundary-scan chain.

•	You can apply test vectors from a JEDEC file through the boundary-scan TAP to CPLDs using the INTEST instruction.

See Also

 "Using JTAG Programmer Batch Version Software"

 "Command-Line Options"

 "Interactive Mode Commands"


Using JTAG Programmer Batch Version Software

JTAG Programmer Files

You must become familiar with the following files, which are used by the JTAG Programmer software.

design.jed

The design.jed file contains the configuration information for the target design in JEDEC 3-C standard formats. The file is generated by the fitter software. This file may optionally contain functional test vectors to do functional verification of XC9500/XL/XV devices.

design.bit

BIT files are Xilinx FPGA configuration files generated by the Xilinx FPGA design software. They are proprietary format binary files containing configuration information. One design.bit file is required for each Xilinx FPGA in the JTAG boundary-scan chain.

jtagprogrammer.pro

The jtagprogrammer.pro file contains the default values for all JTAG Programmer options: part, design, baud, and port. These option values are updated at the end of every JTAG Programmer session. For JTAG Programmer to recognize a jtagprogrammer.pro file, it must be located in the current working directory.

batch_file.cmd

The batch files are text files used to execute commands in the batch mode, and the extension ".cmd" is required.

device.bsd

The bsd files contain Boundary Scan Description Language (BSDL) specifications of the operation of the boundary-scan logic of a given device. For any non-Xilinx device in your boundary-scan chain, you are required to supply this file.

Invoking JTAG Programmer

You can start JTAG Programmer using interactive commands from the system shell. This mode offers additional commands for download and readback and also allows you to probe the internal logic states of the target system device.

Downloading

You can download a design after connecting the cable to the host system and target system. To download a design, enter the following command at the operating system prompt.

jtagprog

When you do not specify any options, the JTAG Programmer software selects the port where the cable is connected and sets the baud rate to the maximum allowed by the platform. You can modify the communication port and baud rate by changing the appropriate settings in the xchecker.pro file.

1.	To download in an interactive mode, enter the following command at the system prompt.

jtagprog

You see the following message on the screen:

JTAGProgrammer: version x1_1.0 Copyright: 1991-1996

Cable ID type is 'XCHECKER'
Cable is connected to '/dev/ttya'
Baud rate is 38400

2.	To specify the number, type, names and order of devices in the boundary-scan chain:

part part_type:design_name

3.	To erase and program the a design, enter this command string:

program design_name

Verifying

After you have properly configured a device, you can verify its configuration and compare it to your original design.

In most applications, verification is not needed, but this feature can be helpful with designs that experience extremely unstable or noisy VCC conditions.

To execute a readback after the device has been in operation, use the interactive commands, as follows:

jtagprog

This command invokes the interactive mode, and the [JTAGProgrammer::(#)] >  prompt appears (the "#" in the prompt string is the current command number).

[JTAGProgrammer::(#)] > part part_type:design_name

The part commands identifies the number the number, type, name and order of devices in the boundary-scan chain. In this case there is one device only. Then to program the device, enter:

[JTAGProgrammer::(#)] > program design_name

The program command downloads design.jed to the target device. If you want a readback after the target device is in operation, you can execute the Verify command.

[JTAGProgrammer::(#)] > verify design_name

This command initiates a readback, and compares the data to the design.jed file.

You may also execute the program and verify operations in one step by typing:

[JTAGProgrammer::(#)] > program -v design_name


Command-Line Options

The following describes the JTAG Programmer command-line options. The data files are configuration bitstream files in JEDEC format. When you do not specify any options or data files, the system defaults to the interactive mode.

The command-line syntax is as follows:

jtagprog options

Note:  You can abbreviate all options to the minimum number of distinctive characters in the option name.

Note:  Commands and options are not case-sensitive.

-batch Batch Mode Operation

Syntax: 	-batch bat_file.cmd

Abbreviation	: b

The Batch option executes commands in batch mode. The bat_file must have a ".cmd" extension and contain valid JTAG Programmer commands, including interactive commands. You can add comments to files by using the # symbol, either on the command line or on a new line.

-h The Help Option

Syntax: 	-help

Abbreviation: 	h

The Help option displays command line usage information.

-log Specify Log File Name

Syntax: 	-log filename.log

Abbreviation: 	-l

Captures all output to the specified log file.

-port Specify Port Name

Syntax: 	-port portname

Abbreviation: 	po

The Specify Port Name option identifies the port connection for the XChecker cable. If you do not specify this option, the default option AUTO, searches for the cable connected to any port, parallel or serial. Valid ports for supported platforms are listed below:

Platform	Communication Ports
IBM PC	com1	com2	lpt1*	lpt2*
Sun	/dev/ttya**	/dev/ttyb**
HP	/dev/tty00	/dev/tty01
*Use with the parallel download cable only.

**ttya and ttyb must be readable and writable to ensure a proper connection.

See Also

 "Interactive Mode Commands"

 "Using the Command Line Interface"


Interactive Mode Commands

This section describes the JTAG Programmer interactive mode commands. To use the interactive mode commands, you enter jtagprog at the system prompt.

Note:  You can abbreviate the commands using the least number of distinctive characters, as with the command line options, but you must use at least two characters. You can repeat the previous command using either an equal sign, "=," or an exclamation point, "!."

Autoconfigure — Identify Chain Composition

Syntax: autoconfigure

Abbreviation: autoc

This command queries all the devices in the chain and attempts t o identify the boundary-scan chain composition using the IDCODE instruction. The command returns a list of devices in the chain and their position with device 1 being closest to the system TDI. Parts that have not implemented IDCODE or those parts whose IDCODE is unrecognized will be identified as unknown devices.

Batch — Execute in Batch Mode

Syntax: 	batch bat_file.cmd

Abbreviation: 	bat

The Batch command executes commands in a batch mode. The  bat_file must have a ".cmd" extension and contain valid JTAG Programmer commands. Use the pound sign, "#" to precede comment lines in the batch file.

Examples

The following examples show two methods of using the Batch command from the JTAG Programmer prompt:

 batch bat_file.cmd

< bat_file.cmd

Baud — Specify Baud Rate

Syntax	: baud baud_rate

Abbreviation: bau

The Baud command specifies a communication baud rate. At initialization, the fastest baud rate for your host system is automatically selected. The table below lists the valid baud rates.

Platform	Baud Rate
	9600	19200	38400
IBM PC	X	X	X
Sun	X	X	X
HP 700	X	X	X
Dump

Syntax: 	dump [-h] part_name  -j  file_name

Abbreviation

The dump command will read the contents of a part and create a JEDEC file with the results. The file created will default to part_name.jed. Optionally, you may specify your own name using the -j flag. The part_name must have been specified with the part command.

The -h flag specifies that all untargeted parts should use HIGHZ mode as the BYPASS method. This will float all untargeted device output pins and can reduce system noise in active environments.

Erase

Syntax: 	erase [-f] [-h] part_name

Abbreviation

This command erases the programmed contents of the specified part. The part_name must have been specified with the part command. The option -f is used to reset write-protect.

The -h flag specifies that all untargeted parts should use HIGHZ mode as the BYPASS method. This will float all untargeted device output pins and can reduce system noise in active environments.

Exit — Terminate Session

Syntax: 	exit

Abbreviation: 	exi

The Exit command terminates the current JTAG Programmer session, asks you whether to save current program options in the xchecker.pro file, and returns you to the system shell.

Functest

Syntax	: functest [-h] part_name [-j file_name]

Abbreviation	: no abbreviation

The functest command will run the functional vectors in the associated JEDEC file (file_name) on the specified device (part_name) using the intest command.  If the part_name is the same as the JEDEC file_name, then the file_name does not need to be specified. The part_name must have been specified with the part command.

The -h flag specifies that all untargeted parts should use HIGHZ mode as the BYPASS method. This will float all untargeted device output pins and can reduce system noise in active environments.

Help — Online Help

Syntax	: help topic

Abbreviation: 	he

The Help command displays online help for the topic requested in 24-line segments. Enter y to scroll forward to the next 24 lines. Enter n to exit Help.

Log — Send Screen Display to File

Syntax: 	log -out file_name string

Abbreviation: 	log

The Log command sends the screen output to the file_name file. Use this command to capture the output of a Readback or a Show command.

There is one option for the Log command.

-out

The -out option closes any previous log file, opens a new one, and places the string at the beginning of the file.

There is one variable for the Log command:

string

 Use the variable string to insert your comments into the log file, which normally only captures the screen display.

Opgroup — Setup Group for Concurrent Operations

Syntax: 	opgroup groupname partname:jedec_file

Abbreviation: 	none

This command is used to set up groups of devices for concurrent operations. Each group specified must have a unique name and can include any number of devices in the boundary-scan chain. The devices are identified by using the partname specified in the part command. You may optionally specify a full path name to the jedec file for each partname.

The opgroup command can be invoked only after a part command has been issued.

The groupname designated in the opgroup command can be used in place of the partname in the erase, program or verify commands to execute concurrent operations on all devices in that group.

Part — Specify Device Chain

Syntax: 	part device_type:part_name device_type:part_name ...

Abbreviation	: pa

This command must be executed first. It describes the devices in the chain to the software. The device_type is used to find the BSDL file associated with each part. BSDL files must be named device_type.bsd. The part_name is an arbitrary name to associate with the device instance in the chain. It will usually be the proper name (the file name without the extension) of the JEDEC file associated with the device at that location in the boundary-scan chain, although it could be anything. The boundary scan chain order must start with the closest device to TDI, and proceed in order through the chain until it reaches the last device, which is closest to TDO. When multiple "part" commands are issued, the information associated with the very last is maintained.

Partinfo

Syntax: 	partinfo [-h] -id -signature -checksum part_name -j jedec_file_name

Abbreviation

The partinfo command returns the manufacturer's identification (id), the user signature (-signature) or the device checksum (-checksum) for a particular part_name. Any or all of the three switches may be specified in a single command. The part_name must have been specified in the part command. When calculating the checksum the JEDEC file should be specified as well to indicate the expected checksum.

The -h flag specifies that all untargeted parts should use HIGHZ mode as the BYPASS method. This will float all untargeted device output pins and can reduce system noise in active environments.

Port — Specify Download/Readback Port

Syntax: 	port portname

Abbreviation: 	po

The port command specifies the download/readback port. The table below lists the valid entries; the ports listed in bold face are the defaults. If the port is defined as Auto, all ports are scanned to search for a cable.

Platform	Communication Ports
IBM PC	com1	com2	lpt1*	lpt2*
Sun	/dev/ttya**	/dev/ttyb**
HP700	/dev/tty00	/dev/tty01
*Use with the parallel download cable only.

**ttya and ttyb must be readable and writable to ensure a proper connection.

Program

Syntax: 	program [-v] [-t] [-s] [-p] [-h] part_name [-j file_name]

Abbreviation

This command programs the specified part. If the part_name is the same as the JEDEC file_name, then the file_name does not need to be specified. The part_name must have been set in the part command. There are four options that may be specified (individually or together):

-v after programming the device reads back the contents and verifies that they agree with the associated JEDEC file.

-t executes a functional test after programming using the vectors contained in the associated JEDEC file.

-s sets data security in the device. This disables readback of the device's programmed contents. The device must be erased to reprogram it.

-p sets data protect in the device. This disables over-write of the device`s programmed contents. The device cannot be erased or re-programmed.

-b skips the erase of the device prior to programming.

-h specifies that all untargeted parts should use HIGHZ mode as the BYPASS method. This will float all untargeted device output pins and can reduce system noise in active environments.

Quit — Terminate Session

Syntax: 	quit

Abbreviation: 	qu

The Quit command terminates the current JTAG Programmer session and asks you whether to save current program options in the xchecker.pro file.

Reset — Reset Target LCA/Cable

Syntax: 	reset [-cable]

Abbreviation: 	res

The Reset command resets the boundary-scan TAP state machines or the XChecker cable. The default is to reset the boundary-scan TAP state machines.

There is one option for the Reset command.

-cable

The -cable option reprograms the XChecker cable's internal FPGA. It re-initializes the cable, including setting the correct baud rate. This option is useful in the event of power glitches that could affect proper cable operation.

With this option, you could remove power from the target system, then restore power, while running JTAG Programmer; the Reset command re-initializes the cable to the proper settings.

Save — Save Option Settings

Syntax: 	save

Abbreviation: 	sa

The Save command saves the settings of four interactive command results in the jtagprogrammer.pro file; baud rate (Baud command), design name (Load command), device type (Parttype command) and port name (Port command).

At initialization, JTAG Programmer reads the jtagprogrammer.pro file to set up the defaults for the current session. This file must be in the current directory or in the XILINX environment search path. JTAG Programmer updates the profile information at the end of every session. The jtagprogrammer.pro file is created when you exit from your first JTAG Programmer session.

Settings — Display Settings

Syntax: 	settings

Abbreviation: 	se

The Settings command provides a listing of the following information; the port name, the baud rate, the type of cable, the design name, the part type and package type, the clock source, and hardware trigger status. It also lists the number of clocks for the first and subsequent snapshots, the number of signals defined in the probe list, and the number of signals defined in the display list.

Sys —Temporarily Exit to Operating System

Syntax: 	sys

Abbreviation: 	none

The Sys command allows you to temporarily exit from JTAG Programmer to the operating system prompt. Enter exit to return to JTAG Programmer.

Verify — Verify Target CPLD Bitstream

Syntax: 	verify [-h] part_name [-j file_name]

Abbreviation: 	ve

This command reads back the configuration registers of the specified part and compares its contents against the JEDEC file. If the part_name is the same as the JEDEC file_name, the file_name does not need to be specified.

The -h flag specifies that all untargeted parts should use HIGHZ mode as the BYPASS method. This will float all untargeted device output pins and can reduce system noise in active environments.


Program Options

The Program Options menu offers five options that will be performed during programming if selected. They are:

•	Erase Before Programming - erases the part before performing any programming (CPLD only).

•	Verify - after programming the device, the JTAG Programmer reads back the contents and verifies that they agree with the associated JEDEC file(Virtex and CPLD only).

•	Functional Test - executes a functional test after programming using the vectors contained in the associated JEDEC file (CPLD only).

•	Write Protect - allows only the reading of the programmed data. The device contents cannot be altered or re-programmed (CPLD only).

•	Read Protect - disables reading the programmed contents of a device (the Device ID and usercode/signature and boundary scan register remain readable) (CPLD only).

Note:  When both Read Protect and Write Protect are enabled, the device can be neither read nor re-programmed.

See Also

 "Data Security Selection"


Erase Options

CPLD data security operations can be overridden only by erasing the device. For Read Protection override, you simply erase the part. For Write Protection override, you must select the override write protect option from the Erase Options dialog box.


Device Properties

You need to specify a JEDEC file for each Xilinx CPLD device in the boundary-scan chain, a BIT file for each Xilinx FPGA, and a BSDL file for all other devices in the boundary-scan chain. Highlight the first device in the chain by clicking once on it and then select the JEDEC or BSDL file corresponding to the device.

Edit → Properties

Alternatively, you may double-click on the device icon.

The Device Properties dialog box appears

Type in the path name or click once on the browse key and find the appropriate file to assign to the highlighted part. Select JEDEC files for each Xilinx CPLD device in the chain, a BIT file for each Xilinx FPGA, and BSDL files for the remaining devices. Repeat for each device in the chain.