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Signals index

Q
 q0 : incmod : wire
Connects down to:mj_s_mux4_d_32:q0mux:in3 , mj_s_ff_snre_d_32:q1reg:out , mj_s_mux4_d_32:a0incmux_0:in3 , mj_s_mux4_d_32:a0incmux_1:in3 
 q0in2 : incmod : wire
Connects down to:mj_s_mux4_d_32:q0mux:in2 
 q1 : incmod : wire
Connects down to:mj_s_mux4_d_32:q1mux:in2 , mj_s_mux4_d_32:q1mux:in3 , mj_s_ff_snre_d_32:q0reg:out , mj_s_mux4_d_32:a1incmux_0:in3 , mj_s_mux4_d_32:a1incmux_1:in3 
 q1in1 : incmod : wire
Connects down to:mj_s_mux4_d_32:q1mux:in1 
 qin : branch_dec : input
Connects down to:mj_s_mux4_d_2:romsel_mux:sel 
Connects up to:code_seq_cntl:branchd:qin 
 qin : code_seq : input
Connects down to:code_seq_cntl:p_code_seq_cntl:qin 
Connects up to:fpu:cs:qin 
 qin : code_seq_cntl : input
Connects down to:branch_dec:branchd:qin 
Connects up to:code_seq:p_code_seq_cntl:qin 
 qin : div_decode : output wire
Connects up to:incmod:divdec:qin 
 qin : fpu : wire
Connects down to:incmod:inc:qin , code_seq:cs:qin 
 qin : incmod : output
Connects down to:div_decode:divdec:qin 
Connects up to:fpu:inc:qin 
 qmd : div_decode : output reg
Connects up to:incmod:divdec:qmd 
 qmd : incmod : wire
Connects down to:div_decode:divdec:qmd , mj_s_mux4_d_32:q1mux:sel , mj_s_mux4_d_32:q0mux:sel 
 qmsb : branch_dec : input
Connects down to:branch_decode1:b1:qmsb , branch_decode2:b2:qmsb , branch_decode3:b3:qmsb , branch_decode4:b4:qmsb 
Connects up to:code_seq_cntl:branchd:qmsb 
 qmsb : branch_decode1 : input
Connects up to:branch_dec:b1:qmsb 
 qmsb : branch_decode2 : input
Connects up to:branch_dec:b2:qmsb 
 qmsb : branch_decode3 : input
Connects up to:branch_dec:b3:qmsb 
 qmsb : branch_decode4 : input
Connects up to:branch_dec:b4:qmsb 
 qmsb : code_seq : input
Connects down to:code_seq_cntl:p_code_seq_cntl:qmsb 
Connects up to:fpu:cs:qmsb 
 qmsb : code_seq_cntl : input
Connects down to:branch_dec:branchd:qmsb 
Connects up to:code_seq:p_code_seq_cntl:qmsb 
 qmsb : fpu : wire
Connects down to:incmod:inc:qmsb , code_seq:cs:qmsb 
 qmsb : incmod : output
Connects up to:fpu:inc:qmsb 
 qualify_miss : dcudp_cntl : wire
 qualify_miss : dc_dec : wire
 qualify_miss_int : dcudp_cntl : wire
 qual_iu_flush_e : ic_cntl : wire
 qual_iu_psr_ice : ic_cntl : wire
Connects down to:mj_s_ff_snr_d:qual_iu_psr_ice_reg:in 
 qual_iu_psr_ice_q : ic_cntl : wire
Connects down to:mj_s_ff_snr_d:qual_iu_psr_ice_reg:out 
 qual_iu_psr_ice_sel : ic_cntl : wire
R
 r0md_rom0 : mantissa_dp : reg
Connects down to:mj_s_mux3_d_32:muxr0_rom0:sel , mj_s_mux3_d_32:muxr1_rom0:sel 
 r0md_rom1 : mantissa_dp : reg
Connects down to:mj_s_mux3_d_32:muxr0_rom1:sel , mj_s_mux3_d_32:muxr1_rom1:sel 
 r0out : fpu : wire
Connects down to:rsadd:rsa:r0out , mantissa:man:r0out 
 r0out : mantissa : output
Connects down to:mantissa_dp:i_mantissa_dp:r0out 
Connects up to:fpu:man:r0out 
 r0out : mantissa_dp : output
Connects down to:mj_s_ff_snre_d_32:ff_r0out:out 
Connects up to:mantissa:i_mantissa_dp:r0out 
 r0out : rsadd : input
Connects down to:rsadd_dp:p_rsadd_dp:r0out 
Connects up to:fpu:rsa:r0out 
 r0out : rsadd_dp : input
Connects down to:rshifter:rshift1:low 
Connects up to:rsadd:p_rsadd_dp:r0out 
 r1out : fpu : wire
Connects down to:rsadd:rsa:r1out , mantissa:man:r1out 
 r1out : mantissa : output
Connects down to:mantissa_dp:i_mantissa_dp:r1out 
Connects up to:fpu:man:r1out 
 r1out : mantissa_dp : output
Connects down to:mj_s_ff_snre_d_32:ff_r1out:out 
Connects up to:mantissa:i_mantissa_dp:r1out 
 r1out : rsadd : input
Connects down to:rsadd_dp:p_rsadd_dp:r1out 
Connects up to:fpu:rsa:r1out 
 r1out : rsadd_dp : input
Connects down to:rshifter:rshift1:high 
Connects up to:rsadd:p_rsadd_dp:r1out 
 r236 : ucode_dat : wire
Connects down to:mj_s_mux6_d_32:mux6_m_adder_porta:in5 , mj_s_mux8_d_32:mux8_m_adder_portb:in4 , buf_cf_32:buf_cf_32_u_ptc:inp , mj_s_mux4_d_32:mux4_r236:mx_out 
 ra : imdr_dpath : wire
Connects down to:mx4_clr_reg_32:mx4_clr_reg_32_a:inp1 , mx4_clr_reg_32:mx4_clr_reg_32_a:inp0 , mx4_clr_reg_32:mx4_clr_reg_32_a:out , an2_32:an2_32_0:inp0 , mx2_33:mx2_33_b:inp1 , mx2_compl_32:mx2_compl_32_a:inp0 , sign_bit:sign_bit_0:ra_31 
 rac : imdr_dpath : wire
Connects down to:mx4_clr_reg_33:mx4_clr_reg_33_ac:inp0 , mx4_clr_reg_33:mx4_clr_reg_33_ac:out , mx2i_33:mx2i_33_a:inp1 , rsh16_33:rsh16_33_b:hi 
 ram : rf : reg
 ram_ld_rdy_e : dc_dec : wire
 ram_st_rdy_e : dc_dec : wire
 ram_st_rdy_e_in : dc_dec : wire
 rand1 : memc : integer
 rand2 : memc : integer
 random_int_cyc : powerdown_monitor : reg
 random_int_reg : powerdown_monitor : reg
 random_sel : powerdown_monitor : reg
 rand_smu_start : picoJavaII : reg
 rand_time : picoJavaII : reg
 range1_h_cmp1_eq : ex : wire
Connects down to:ex_ctl:ex_ctl:range1_h_cmp1_eq , ex_regs:ex_regs:range1_h_cmp1_eq 
 range1_h_cmp1_eq : ex_ctl : input
Connects up to:ex:ex_ctl:range1_h_cmp1_eq 
 range1_h_cmp1_eq : ex_regs : output
Connects down to:ucmp_16:range1_h_cmp1:eq 
Connects up to:ex:ex_regs:range1_h_cmp1_eq 
 range1_h_cmp1_gt : ex : wire
Connects down to:ex_ctl:ex_ctl:range1_h_cmp1_gt , ex_regs:ex_regs:range1_h_cmp1_gt 
 range1_h_cmp1_gt : ex_ctl : input
Connects up to:ex:ex_ctl:range1_h_cmp1_gt 
 range1_h_cmp1_gt : ex_regs : output
Connects down to:ucmp_16:range1_h_cmp1:gt 
Connects up to:ex:ex_regs:range1_h_cmp1_gt 
 range1_h_cmp1_lt : ex_regs : wire
Connects down to:ucmp_16:range1_h_cmp1:lt 
 range1_h_cmp2_eq : ex : wire
Connects down to:ex_ctl:ex_ctl:range1_h_cmp2_eq , ex_regs:ex_regs:range1_h_cmp2_eq 
 range1_h_cmp2_eq : ex_ctl : input
Connects up to:ex:ex_ctl:range1_h_cmp2_eq 
 range1_h_cmp2_eq : ex_regs : output
Connects down to:ucmp_16:range1_h_cmp2:eq 
Connects up to:ex:ex_regs:range1_h_cmp2_eq 
 range1_h_cmp2_gt : ex : wire
Connects down to:ex_ctl:ex_ctl:range1_h_cmp2_gt , ex_regs:ex_regs:range1_h_cmp2_gt 
 range1_h_cmp2_gt : ex_ctl : input
Connects up to:ex:ex_ctl:range1_h_cmp2_gt 
 range1_h_cmp2_gt : ex_regs : output
Connects down to:ucmp_16:range1_h_cmp2:gt 
Connects up to:ex:ex_regs:range1_h_cmp2_gt 
 range1_h_cmp2_lt : ex_regs : wire
Connects down to:ucmp_16:range1_h_cmp2:lt 
 range1_l_cmp1_eq : ex_regs : wire
Connects down to:ucmp_16:range1_l_cmp1:eq 
 range1_l_cmp1_gt : ex_regs : wire
Connects down to:ucmp_16:range1_l_cmp1:gt 
 range1_l_cmp1_lt : ex : wire
Connects down to:ex_ctl:ex_ctl:range1_l_cmp1_lt , ex_regs:ex_regs:range1_l_cmp1_lt 
 range1_l_cmp1_lt : ex_ctl : input
Connects up to:ex:ex_ctl:range1_l_cmp1_lt 
 range1_l_cmp1_lt : ex_regs : output
Connects down to:ucmp_16:range1_l_cmp1:lt 
Connects up to:ex:ex_regs:range1_l_cmp1_lt 
 range1_l_cmp2_eq : ex_regs : wire
Connects down to:ucmp_16:range1_l_cmp2:eq 
 range1_l_cmp2_gt : ex_regs : wire
Connects down to:ucmp_16:range1_l_cmp2:gt 
 range1_l_cmp2_lt : ex : wire
Connects down to:ex_ctl:ex_ctl:range1_l_cmp2_lt , ex_regs:ex_regs:range1_l_cmp2_lt 
 range1_l_cmp2_lt : ex_ctl : input
Connects up to:ex:ex_ctl:range1_l_cmp2_lt 
 range1_l_cmp2_lt : ex_regs : output
Connects down to:ucmp_16:range1_l_cmp2:lt 
Connects up to:ex:ex_regs:range1_l_cmp2_lt 
 range2_h_cmp1_eq : ex : wire
Connects down to:ex_ctl:ex_ctl:range2_h_cmp1_eq , ex_regs:ex_regs:range2_h_cmp1_eq 
 range2_h_cmp1_eq : ex_ctl : input
Connects up to:ex:ex_ctl:range2_h_cmp1_eq 
 range2_h_cmp1_eq : ex_regs : output
Connects down to:ucmp_16:range2_h_cmp1:eq 
Connects up to:ex:ex_regs:range2_h_cmp1_eq 
 range2_h_cmp1_gt : ex : wire
Connects down to:ex_ctl:ex_ctl:range2_h_cmp1_gt , ex_regs:ex_regs:range2_h_cmp1_gt 
 range2_h_cmp1_gt : ex_ctl : input
Connects up to:ex:ex_ctl:range2_h_cmp1_gt 
 range2_h_cmp1_gt : ex_regs : output
Connects down to:ucmp_16:range2_h_cmp1:gt 
Connects up to:ex:ex_regs:range2_h_cmp1_gt 
 range2_h_cmp1_lt : ex_regs : wire
Connects down to:ucmp_16:range2_h_cmp1:lt 
 range2_h_cmp2_eq : ex : wire
Connects down to:ex_ctl:ex_ctl:range2_h_cmp2_eq , ex_regs:ex_regs:range2_h_cmp2_eq 
 range2_h_cmp2_eq : ex_ctl : input
Connects up to:ex:ex_ctl:range2_h_cmp2_eq 
 range2_h_cmp2_eq : ex_regs : output
Connects down to:ucmp_16:range2_h_cmp2:eq 
Connects up to:ex:ex_regs:range2_h_cmp2_eq 
 range2_h_cmp2_gt : ex : wire
Connects down to:ex_ctl:ex_ctl:range2_h_cmp2_gt , ex_regs:ex_regs:range2_h_cmp2_gt 
 range2_h_cmp2_gt : ex_ctl : input
Connects up to:ex:ex_ctl:range2_h_cmp2_gt 
 range2_h_cmp2_gt : ex_regs : output
Connects down to:ucmp_16:range2_h_cmp2:gt 
Connects up to:ex:ex_regs:range2_h_cmp2_gt 
 range2_h_cmp2_lt : ex_regs : wire
Connects down to:ucmp_16:range2_h_cmp2:lt 
 range2_l_cmp1_eq : ex_regs : wire
Connects down to:ucmp_16:range2_l_cmp1:eq 
 range2_l_cmp1_gt : ex_regs : wire
Connects down to:ucmp_16:range2_l_cmp1:gt 
 range2_l_cmp1_lt : ex : wire
Connects down to:ex_ctl:ex_ctl:range2_l_cmp1_lt , ex_regs:ex_regs:range2_l_cmp1_lt 
 range2_l_cmp1_lt : ex_ctl : input
Connects up to:ex:ex_ctl:range2_l_cmp1_lt 
 range2_l_cmp1_lt : ex_regs : output
Connects down to:ucmp_16:range2_l_cmp1:lt 
Connects up to:ex:ex_regs:range2_l_cmp1_lt 
 range2_l_cmp2_eq : ex_regs : wire
Connects down to:ucmp_16:range2_l_cmp2:eq 
 range2_l_cmp2_gt : ex_regs : wire
Connects down to:ucmp_16:range2_l_cmp2:gt 
 range2_l_cmp2_lt : ex : wire
Connects down to:ex_ctl:ex_ctl:range2_l_cmp2_lt , ex_regs:ex_regs:range2_l_cmp2_lt 
 range2_l_cmp2_lt : ex_ctl : input
Connects up to:ex:ex_ctl:range2_l_cmp2_lt 
 range2_l_cmp2_lt : ex_regs : output
Connects down to:ucmp_16:range2_l_cmp2:lt 
Connects up to:ex:ex_regs:range2_l_cmp2_lt 
 raw_iu_ld_e : dc_dec : wire
 ra_31 : sign_bit : input
Connects up to:imdr_dpath:sign_bit_0:ra 
 ra_booth : imdr_dpath : wire
Connects down to:mx2_33:mx2_33_b:out , mx2_neg_33:mx2_neg_33_a:inp0 
 rb : imdr_dpath : wire
Connects down to:mx4_clr_reg_32:mx4_clr_reg_32_b:inp0 , mx4_clr_reg_32:mx4_clr_reg_32_b:out , rsh16_33:rsh16_33_b:lo , mx2_33:mx2_33_c:inp0 , compl_32:compl_32_b:inp , sign_bit:sign_bit_0:rb_31 
 rbb : imdr_dpath : wire
Connects down to:mx4_clr_reg_nxt_32:mx4_clr_reg_nxt_32_bb:inp1 , mx4_clr_reg_nxt_32:mx4_clr_reg_nxt_32_bb:inp0 , mx4_clr_reg_nxt_32:mx4_clr_reg_nxt_32_bb:out , dpath_ctrl:dpath_ctrl_0:rbb1 
 rbb1 : dpath_ctrl : input
Connects up to:imdr_dpath:dpath_ctrl_0:rbb 
 rb_31 : sign_bit : input
Connects up to:imdr_dpath:sign_bit_0:rb 
 rcu : monitor : wire
Connects down to:ucode_monitor:ucode_monitor:u_addr_st_wt 
 rcu_dpath : monitor : wire
Connects down to:ucode_monitor:ucode_monitor:u_addr_st_wt 
 ready_to_powerdown : pcsu : wire
 read_const_pool : ex_ctl : wire
 read_d_cache : ucode_monitor : wire
 read_frame : ex_ctl : wire
 read_gl0 : decode_opcode : output
Connects up to:rcu_ctl:decode_opcode_rs1:read_gl0_rs1 , rcu_ctl:decode_opcode_rs2:read_gl0_rs2 
 read_gl0 : rs1_dec : wire
 read_gl0 : rs2_dec : wire
 read_gl0_rs1 : rcu_ctl : wire
Connects down to:decode_opcode:decode_opcode_rs1:read_gl0 
 read_gl0_rs2 : rcu_ctl : wire
Connects down to:decode_opcode:decode_opcode_rs2:read_gl0 
 read_gl1 : decode_opcode : output
Connects up to:rcu_ctl:decode_opcode_rs1:read_gl1_rs1 , rcu_ctl:decode_opcode_rs2:read_gl1_rs2 
 read_gl1 : rs1_dec : wire
 read_gl1 : rs2_dec : wire
 read_gl1_rs1 : rcu_ctl : wire
Connects down to:decode_opcode:decode_opcode_rs1:read_gl1 
 read_gl1_rs2 : rcu_ctl : wire
Connects down to:decode_opcode:decode_opcode_rs2:read_gl1 
 read_gl2 : decode_opcode : output
Connects up to:rcu_ctl:decode_opcode_rs1:read_gl2_rs1 , rcu_ctl:decode_opcode_rs2:read_gl2_rs2 
 read_gl2 : rs1_dec : wire
 read_gl2 : rs2_dec : wire
 read_gl2_rs1 : rcu_ctl : wire
Connects down to:decode_opcode:decode_opcode_rs1:read_gl2 
 read_gl2_rs2 : rcu_ctl : wire
Connects down to:decode_opcode:decode_opcode_rs2:read_gl2 
 read_gl3 : decode_opcode : output
Connects up to:rcu_ctl:decode_opcode_rs1:read_gl3_rs1 , rcu_ctl:decode_opcode_rs2:read_gl3_rs2 
 read_gl3 : rs1_dec : wire
 read_gl3 : rs2_dec : wire
 read_gl3_rs1 : rcu_ctl : wire
Connects down to:decode_opcode:decode_opcode_rs1:read_gl3 
 read_gl3_rs2 : rcu_ctl : wire
Connects down to:decode_opcode:decode_opcode_rs2:read_gl3 
 read_global0 : ex_ctl : wire
 read_global1 : ex_ctl : wire
 read_global2 : ex_ctl : wire
 read_global3 : ex_ctl : wire
 read_icache_data : rs1_dec : wire
 read_icache_tag : rs1_dec : wire
 read_optop : ex_ctl : wire
 read_pc : ex_ctl : wire
 read_ptr : fram32_8 : input
 read_ptr : fram37_8 : input
 read_ptr : fram48_8 : input
 read_ptr : fram58_4 : input
 read_vars : ex_ctl : wire
 real_wb_req : dcctl : wire
Connects down to:dcudp_cntl:dcudp_cntl:wb_req , wrbuf_cntl:wrbuf_cntl:real_wb_req 
 real_wb_req : wrbuf_cntl : output
Connects up to:dcctl:wrbuf_cntl:real_wb_req 
 recording_on : picoJavaII : integer
 recording_times : picoJavaII : reg
 record_on : picoJavaII_pin_recorder : reg
 reg0 : fram32_8 : reg
 reg0 : fram37_8 : reg
 reg0 : fram48_8 : reg
 reg0 : fram58_4 : reg
 reg0 : ucode_dat : wire
Connects down to:mj_s_mux8_d_32:mux8_a_oprd:in0 , del1_32:del1_32_reg0:inp , ff_sre_32:reg_reg0:out 
 reg1 : fram32_8 : reg
 reg1 : fram37_8 : reg
 reg1 : fram48_8 : reg
 reg1 : fram58_4 : reg
 reg1 : ucode_dat : wire
Connects down to:mj_s_mux8_d_32:mux8_a_oprd:in1 , del1_32:del1_32_reg1:inp , ff_sre_32:reg_reg1:out 
 reg2 : fram32_8 : reg
 reg2 : fram37_8 : reg
 reg2 : fram48_8 : reg
 reg2 : fram58_4 : reg
 reg2 : ucode_dat : wire
Connects down to:mj_s_mux8_d_32:mux8_a_oprd:in2 , del1_32:del1_32_reg2:inp , ff_sre_32:reg_reg2:out , mj_s_mux4_d_32:mux4_r236:in0 
 reg3 : fram32_8 : reg
 reg3 : fram37_8 : reg
 reg3 : fram48_8 : reg
 reg3 : fram58_4 : reg
 reg3 : ucode_dat : wire
Connects down to:mj_s_mux8_d_32:mux8_a_oprd:in3 , del1_32:del1_32_reg3:inp , ff_sre_32:reg_reg3:out , mj_s_mux4_d_32:mux4_r236:in1 
 reg4 : fram32_8 : reg
 reg4 : fram37_8 : reg
 reg4 : fram48_8 : reg
 reg5 : fram32_8 : reg
 reg5 : fram37_8 : reg
 reg5 : fram48_8 : reg
 reg5 : ucode_dat : wire
Connects down to:mj_s_mux8_d_32:mux8_a_oprd:in4 , mj_s_mux8_d_32:mux8_b_oprd:in1 , del1_32:del1_32_reg5:inp , ff_sre_32:reg_reg5:out 
 reg5_31 : ucode : wire
Connects down to:ucode_ctrl:ucode_ctrl_0:reg5_31 , ucode_dpath:ucode_dpath_0:reg5_31 
 reg5_31 : ucode_ctrl : input
Connects down to:ucode_seq:ucode_seq_0:reg5_31 
Connects up to:ucode:ucode_ctrl_0:reg5_31 
 reg5_31 : ucode_dat : output
Connects up to:ucode_dpath:ucode_dat_0:reg5_31 
 reg5_31 : ucode_dpath : output
Connects down to:ucode_dat:ucode_dat_0:reg5_31 
Connects up to:ucode:ucode_dpath_0:reg5_31 
 reg5_31 : ucode_seq : input
Connects up to:ucode_ctrl:ucode_seq_0:reg5_31 
 reg6 : fram32_8 : reg
 reg6 : fram37_8 : reg
 reg6 : fram48_8 : reg
 reg6 : ucode_dat : wire
Connects down to:mj_s_mux8_d_32:mux8_b_oprd:in2 , del1_32:del1_32_reg6:inp , ff_sre_32:reg_reg6:out , mj_s_mux4_d_32:mux4_r236:in2 
 reg7 : fram32_8 : reg
 reg7 : fram37_8 : reg
 reg7 : fram48_8 : reg
 region1 : ucode_seq : wire
 region2 : ucode_seq : wire
 region_eq : ucode_seq : wire
 register_changed : ucode_monitor : integer
 reg_clear_l : ucode_dat : wire
Connects down to:ff_sre_32:reg_areg0:reset_l , ff_sre_32:reg_reg0:reset_l , ff_sre_32:reg_reg1:reset_l , ff_sre_32:reg_reg2:reset_l , ff_sre_32:reg_reg3:reset_l , ff_sre_32:reg_reg5:reset_l , ff_sre_32:reg_reg6:reset_l 
 reg_clear_l : ucode_seq : wire
Connects down to:ff_sre_9:seq_addr1_reg:reset_l , ff_sre_9:seq_addr2_reg:reset_l , ff_sre_9:seq_addr3_reg:reset_l , ff_sre:last_reg:reset_l , ff_sre:abt_rdwt_reg:reset_l , ff_sre:abt_cur_reg:reset_l , ff_sre:ary_null_reg:reset_l , ff_sre:ary_ovf_reg:reset_l , ff_sre:ptr_un_eq_reg:reset_l , ff_sre:ptr_gc_notify:reset_l 
 reg_data_e : ex : wire
Connects down to:ex_dpath:ex_dpath:reg_data_e , ex_regs:ex_regs:data_out 
 reg_data_e : ex_dpath : input
Connects down to:mux8_32:alu_out_mux:in5 
Connects up to:ex:ex_dpath:reg_data_e 
 reg_enable : dcram_dummy : input
 reg_enable : dcram_shell : input
Connects down to:dcram_top:dcram_top:enable 
 reg_enable : dtag_dummy : input
 reg_enable : dtag_shell : input
Connects down to:dtag_top:dtag_top:enable 
 reg_enable : monitor : wire
Connects down to:ucode_monitor:ucode_monitor:reg_enable 
 reg_enable : ucode_monitor : input
Connects up to:monitor:ucode_monitor:ucode_seq_0 , monitor:ucode_monitor:reg_enable , monitor:ucode_monitor:ucode_ctrl_0 
 reg_enable : ucode_seq : wire
Connects down to:ff_sre_9:seq_addr1_reg:enable , ff_sre_9:seq_addr2_reg:enable , ff_sre_9:seq_addr3_reg:enable , ff_se:done_reg:enable , ff_sre:last_reg:enable , ff_sre:ary_null_reg:enable , ff_sre:ary_ovf_reg:enable , ff_sre:ptr_un_eq_reg:enable , ff_sre:ptr_gc_notify:enable 
 reg_rd_mux_sel : ex : wire
Connects down to:ex_ctl:ex_ctl:reg_rd_mux_sel , ex_regs:ex_regs:reg_rd_mux_sel 
 reg_rd_mux_sel : ex_ctl : output
Connects up to:ex:ex_ctl:reg_rd_mux_sel 
 reg_rd_mux_sel : ex_regs : input
Connects down to:mux21_32:reg_rd_mux:sel 
Connects up to:ex:ex_regs:reg_rd_mux_sel 
 reg_rd_mux_sel_r : ex_ctl : wire
Connects down to:ff_sre_21:reg_rd_mux_sel_raw_e_reg:din 
 reg_rd_mux_sel_raw_e : ex_ctl : wire
Connects down to:ff_sre_21:reg_rd_mux_sel_raw_e_reg:out 
 reg_u_fxx : ucode_reg : wire
Connects down to:del1_32:del1_32_0:inp , del1_32:del1_32_1:inp , del1_16:del1_16_2:inp , ff_s_32:ff_s_32_1:out , ff_s_32:ff_s_32_2:out , ff_s_16:ff_s_16_1:out 
 reg_wr1_mux_sel : ex_ctl : wire
 reg_write : ucode_monitor : wire
 reg_wr_mux_sel : ex : wire
Connects down to:ex_ctl:ex_ctl:reg_wr_mux_sel , ex_regs:ex_regs:reg_wr_mux_sel 
 reg_wr_mux_sel : ex_ctl : output
Connects up to:ex:ex_ctl:reg_wr_mux_sel 
 reg_wr_mux_sel : ex_regs : input
Connects down to:ff_se_30:frame_reg:enable , ff_se_6:psr_dbh_dbl_reg:enable , ff_sre:psr_bm8_reg:enable , ff_se_4:psr_pil_reg:enable , ff_se_21:trapbase_tba_reg:enable , ff_se:lockcount0_lockwant_reg:enable , ff_se:lockcount1_lockwant_reg:enable , ff_se_32:userrange1_reg:enable , ff_se_32:brk1a_reg:enable , ff_se_32:brk2a_reg:enable , ff_se_32:userrange2_reg:enable , mux2_30:la0_reg_din_mux:sel , mux2_30:la1_reg_din_mux:sel 
Connects up to:ex:ex_regs:reg_wr_mux_sel 
 reg_wr_mux_sel_r : ex_ctl : wire
Connects down to:ff_sre_19:reg_wr_mux_sel_raw_e_reg:din 
 reg_wr_mux_sel_raw_e : ex_ctl : wire
Connects down to:ff_sre_19:reg_wr_mux_sel_raw_e_reg:out 
 reissue_c : branch_logic : input
Connects up to:ex_ctl:branch_logic:reissue_c 
 reissue_c : ex : input
Connects down to:ex_ctl:ex_ctl:reissue_c 
Connects up to:iu:ex:reissue_c 
 reissue_c : ex_ctl : input
Connects down to:branch_logic:branch_logic:reissue_c 
Connects up to:ex:ex_ctl:reissue_c 
 reissue_c : iu : wire
Connects down to:ex:ex:reissue_c , pipe:pipe:reissue_c 
 reissue_c : pipe : output
Connects down to:pipe_cntl:pipe_cntl:reissue_c 
Connects up to:iu:pipe:reissue_c 
 reissue_c : pipe_cntl : output
Connects up to:pipe:pipe_cntl:reissue_c 
 rem_cmp : dpath_ctrl : input
Connects up to:imdr_dpath:dpath_ctrl_0:rem_cmp 
 rem_cmp : imdr : wire
Connects down to:imdr_dpath:imdr_dpath_0:rem_cmp , imdr_ctrl:imdr_ctrl_0:rem_cmp 
 rem_cmp : imdr_ctrl : output
Connects up to:imdr:imdr_ctrl_0:rem_cmp 
 rem_cmp : imdr_dpath : input
Connects down to:sign_bit:sign_bit_0:rem_cmp , dpath_ctrl:dpath_ctrl_0:rem_cmp 
Connects up to:imdr:imdr_dpath_0:rem_cmp 
 rem_cmp : sign_bit : input
Connects up to:imdr_dpath:sign_bit_0:rem_cmp 
 rem_e : ex : wire
Connects down to:ex_ctl:ex_ctl:rem_e , imdr:ex_imdr:ie_rem_d 
 rem_e : ex_ctl : output
Connects up to:ex:ex_ctl:rem_e 
 rem_e : imdr_ctrl : wire
Connects down to:ff_sr_3:ff_sr_3_1:out 
 rem_op : branch_dec : input
Connects down to:branch_decode1:b1:rem_op , branch_decode2:b2:rem_op , branch_decode3:b3:rem_op , branch_decode4:b4:rem_op 
Connects up to:code_seq_cntl:branchd:rem_op 
 rem_op : branch_decode1 : input
Connects up to:branch_dec:b1:rem_op 
 rem_op : branch_decode2 : input
Connects up to:branch_dec:b2:rem_op 
 rem_op : branch_decode3 : input
Connects up to:branch_dec:b3:rem_op 
 rem_op : branch_decode4 : input
Connects up to:branch_dec:b4:rem_op 
 rem_op : code_seq_cntl : wire
Connects down to:branch_dec:branchd:rem_op , mj_s_mux2_d_6:fpumux:in0 , mj_s_ff_snre_d_6:conreg:out 
 rem_opp : code_seq_cntl : wire
Connects down to:opcode_dec:d8:rem_opp , mj_s_mux2_d_6:fpumux:in1 
 rem_opp : opcode_dec : output
Connects up to:code_seq_cntl:d8:rem_opp 
 rem_r : ex_ctl : wire
Connects down to:ff_sre:rem_e_flop:din 
 rem_raw_e : ex_ctl : wire
Connects down to:ff_sre:rem_e_flop:out 
 rem_sum32 : dpath_ctrl : output
Connects up to:imdr_dpath:dpath_ctrl_0:rem_sum32 
 rem_sum32 : imdr : wire
Connects down to:imdr_dpath:imdr_dpath_0:rem_sum32 , imdr_ctrl:imdr_ctrl_0:rem_sum32 
 rem_sum32 : imdr_ctrl : input
Connects up to:imdr:imdr_ctrl_0:rem_sum32 
 rem_sum32 : imdr_dpath : output wire
Connects down to:dpath_ctrl:dpath_ctrl_0:rem_sum32 
Connects up to:imdr:imdr_dpath_0:rem_sum32 
 rem_sum32_ : dpath_ctrl : wire
 repl_addr : dcctl : output
Connects down to:wrbuf_cntl:wrbuf_cntl:repl_addr 
Connects up to:dcu_nocache:dcctl:repl_addr , dcu:dcctl:repl_addr 
 repl_addr : dcu : wire
Connects down to:dcctl:dcctl:repl_addr , dcu_dpath:dcu_dpath:repl_addr 
 repl_addr : dcu_dpath : input
Connects up to:dcu_nocache:dcu_dpath:repl_addr , dcu:dcu_dpath:repl_addr 
 repl_addr : dcu_nocache : wire
Connects down to:dcctl:dcctl:repl_addr , dcu_dpath:dcu_dpath:repl_addr 
 repl_addr : wrbuf_cntl : output
Connects up to:dcctl:wrbuf_cntl:repl_addr 
 repl_addr0 : wrbuf_cntl : wire
 repl_addr1 : wrbuf_cntl : wire
 repl_busy : dcctl : wire
Connects down to:dc_dec:dc_dec:repl_busy , dcudp_cntl:dcudp_cntl:repl_busy , wrbuf_cntl:wrbuf_cntl:repl_busy 
 repl_busy : dcudp_cntl : input
Connects up to:dcctl:dcudp_cntl:repl_busy 
 repl_busy : dc_dec : input
Connects up to:dcctl:dc_dec:repl_busy 
 repl_busy : wrbuf_cntl : output
Connects up to:dcctl:wrbuf_cntl:repl_busy 
 repl_line_inv : dcudp_cntl : wire
 repl_start : dcctl : wire
Connects down to:dcudp_cntl:dcudp_cntl:repl_start , wrbuf_cntl:wrbuf_cntl:repl_start , miss_cntl:miss_cntl:repl_start 
 repl_start : dcudp_cntl : output
Connects up to:dcctl:dcudp_cntl:repl_start 
 repl_start : miss_cntl : input
Connects up to:dcctl:miss_cntl:repl_start 
 repl_start : wrbuf_cntl : input
Connects down to:ff_sr:repl_state_reg0:din 
Connects up to:dcctl:wrbuf_cntl:repl_start 
 repl_state : wrbuf_cntl : wire
Connects down to:ff_sr:repl_state_reg0:out , ff_sr:repl_state_reg1:out , ff_sr:repl_state_reg1:din 
 repl_word_addr : dcu_dpath : output
Connects up to:dcu_nocache:dcu_dpath:dcu_addr_c , dcu:dcu_dpath:dcu_addr_c 
 req_addr_sel : dcctl : output
Connects down to:dcudp_cntl:dcudp_cntl:req_addr_sel 
Connects up to:dcu_nocache:dcctl:req_addr_sel , dcu:dcctl:req_addr_sel 
 req_addr_sel : dcu : wire
Connects down to:dcctl:dcctl:req_addr_sel , dcu_dpath:dcu_dpath:req_addr_sel 
 req_addr_sel : dcudp_cntl : output
Connects up to:dcctl:dcudp_cntl:req_addr_sel 
 req_addr_sel : dcu_dpath : input
Connects down to:mux2_32:dcu_biu_adr_mux:sel , mux2_32:dcu_biu_adr_mux:sel 
Connects up to:dcu_nocache:dcu_dpath:req_addr_sel , dcu:dcu_dpath:req_addr_sel 
 req_addr_sel : dcu_nocache : wire
Connects down to:dcctl:dcctl:req_addr_sel , dcu_dpath:dcu_dpath:req_addr_sel 
 req_outstanding : dcctl : wire
Connects down to:dc_dec:dc_dec:req_outstanding , dcudp_cntl:dcudp_cntl:req_outstanding , miss_cntl:miss_cntl:req_outstanding 
 req_outstanding : dcudp_cntl : input
Connects down to:ff_sre:tag_set_reg:enable 
Connects up to:dcctl:dcudp_cntl:req_outstanding 
 req_outstanding : dc_dec : output
Connects down to:ff_sre_8:iu_miss_stall_reg:enable , ff_sre_4:smu_miss_stall_reg:enable , ff_sre_8:iu_miss_reg:enable , ff_sre_4:smu_miss_reg:enable , ff_sre:nc_c2_reg:enable 
Connects up to:dcctl:dc_dec:req_outstanding 
 req_outstanding : miss_cntl : input
Connects up to:dcctl:miss_cntl:req_outstanding 
 reset : bus_monitor : input
Connects up to:monitor:bus_monitor:pj_reset 
 reset : ibuf_monitor : input
Connects up to:monitor:ibuf_monitor:pj_reset 
 reset : memc : input
Connects up to:picoJavaII:memc:pj_reset 
 reset_d1_l : ic_cntl : wire
Connects down to:mj_s_ff_s_d:reset_reg:out 
 reset_internal : memc : reg
 reset_l : acode_dec : input
Connects up to:code_seq_dp:acode:reset_l 
 reset_l : biu : input
Connects down to:biu_ctl:biu_ctl:reset_l 
Connects up to:picoJavaII:biu:pj_reset 
 reset_l : biu_ctl : input
Connects down to:ff_sre:arb_select_state:reset_l , ff_sre_4:arb_state_reg:reset_l , ff_s:arb_state_reg_0:din 
Connects up to:biu:biu_ctl:reset_l 
 reset_l : code_seq : input
Connects down to:code_seq_cntl:p_code_seq_cntl:reset_l , code_seq_dp:p_code_seq_dp:reset_l 
Connects up to:fpu:cs:reset_l 
 reset_l : code_seq_cntl : input
Connects down to:fpu_dec:fpud:reset_l , mj_s_ff_snre_d_6:conreg:reset_l 
Connects up to:code_seq:p_code_seq_cntl:reset_l 
 reset_l : code_seq_dp : input
Connects down to:mj_s_ff_snr_d_8:tba:reset_l , mj_s_ff_snr_d:tbe:reset_l , mj_s_ff_snre_d_64:mw:reset_l , acode_dec:acode:reset_l , mj_s_ff_snre_d_8:ffopcode:reset_l , mj_s_ff_snre_d:ff_opvalid:reset_l , mj_s_ff_snre_d:ff_valid:reset_l , mj_s_ff_snre_d:ff_valid_a:reset_l , mj_s_ff_snre_d_4:link_mod:reset_l 
Connects up to:code_seq:p_code_seq_dp:reset_l 
 reset_l : cpu : input
Connects down to:iu:iu:reset_l , ICU_MODULE:icu:reset_l , DCU_MODULE:dcu:reset_l , smu:smu:reset_l , pcsu:pcsu:reset_l , FPU_MODULE:fpu:reset_l 
 reset_l : dcctl : input
Connects down to:dc_dec:dc_dec:reset_l , dcudp_cntl:dcudp_cntl:reset_l , wrbuf_cntl:wrbuf_cntl:reset_l , miss_cntl:miss_cntl:reset_l 
Connects up to:dcu_nocache:dcctl:reset_l , dcu:dcctl:reset_l 
 reset_l : dcu : input
Connects down to:dcctl:dcctl:reset_l 
 reset_l : dcudp_cntl : input
Connects down to:ff_sr_2:flush_inst_c2_reg:reset_l , ff_sre:tag_set_reg:reset_l , ff_sr:diag_set_sel_reg:reset_l , ff_sr:dcu_addr_c_31_reg:reset_l , ff_sr:flush_set_sel_reg:reset_l , ff_sre_4:cf_word_addr_reg:reset_l , ff_s:cf_word_addr_0_reg:din , mj_spare:spare:reset_l 
Connects up to:dcctl:dcudp_cntl:reset_l 
 reset_l : dcu_nocache : input
Connects down to:dcctl:dcctl:reset_l 
 reset_l : dc_dec : input
Connects down to:ff_sr:squash_inst_reg:reset_l , ff_sr:smu_stall_store_reg:reset_l , ff_sr:miss_stall_vld_reg:reset_l , ff_sre_8:iu_miss_stall_reg:reset_l , ff_sr:smu_miss_stall_vld_reg:reset_l , ff_sre_4:smu_miss_stall_reg:reset_l , ff_sr:smu_na_st_miss_reg:reset_l , ff_sr:smu_na_st_miss_c2_reg:reset_l , ff_sr:iu_reciculating_reg:reset_l , ff_sr:smu_reciculating_reg:reset_l , ff_sre_8:iu_miss_reg:reset_l , ff_sre_4:smu_miss_reg:reset_l , ff_sr:iu_pending_reg:reset_l , ff_sr:smu_pending_reg:reset_l , ff_sre:nc_c2_reg:reset_l , ff_sr:miss_sustain_reg:reset_l , ff_sr:fill_cyc_d1reg:reset_l , ff_sr_3:error_reg:reset_l , ff_sr:pwrdown_reg:reset_l , ff_sr_3:dcu_perf_reg:reset_l 
Connects up to:dcctl:dc_dec:reset_l 
 reset_l : ex : input
Connects down to:ex_ctl:ex_ctl:reset_l , ex_dpath:ex_dpath:reset_l , imdr:ex_imdr:reset_l , ex_regs:ex_regs:reset_l 
Connects up to:iu:ex:reset_l 
 reset_l : exponent : input
Connects down to:exponent_cntl:p_exponent_cntl:reset_l , exponent_dp:p_exponent_dp:reset_l 
Connects up to:fpu:exp:reset_l 
 reset_l : exponent_cntl : input
Connects down to:exptop_dec:exptop:reset_l 
Connects up to:exponent:p_exponent_cntl:reset_l 
 reset_l : exponent_dp : input
Connects down to:mj_s_ff_snre_d_16:ff_excon:reset_l , mj_s_ff_snre_d_16:aex:reset_l , mj_s_ff_snre_d_16:bex:reset_l , mj_s_ff_snre_d_16:sax:reset_l 
Connects up to:exponent:p_exponent_dp:reset_l 
 reset_l : exptop_dec : input
Connects down to:mj_s_ff_snre_d_2:mux1ad_ff:reset_l 
Connects up to:exponent_cntl:exptop:reset_l 
 reset_l : ex_ctl : input
Connects down to:ff_sre:wr_optop_e_flop:reset_l , ff_sr:ret_optop_update_flop:reset_l , ff_sre:ifeq_e_flop:reset_l , ff_sre:if_icmpeq_e_flop:reset_l , ff_sre:if_acmpeq_e_flop:reset_l , ff_sre:ifge_e_flop:reset_l , ff_sre:if_icmpge_e_flop:reset_l , ff_sre:ifle_e_flop:reset_l , ff_sre:if_icmple_e_flop:reset_l , ff_sre:ifnull_e_flop:reset_l , ff_sre:ifne_e_flop:reset_l , ff_sre:if_icmpne_e_flop:reset_l , ff_sre:if_acmpne_e_flop:reset_l , ff_sre:ifnonnull_e_flop:reset_l , ff_sre:ifgt_e_flop:reset_l , ff_sre:if_icmpgt_e_flop:reset_l , ff_sre:iflt_e_flop:reset_l , ff_sre:if_icmplt_e_flop:reset_l , ff_sre:goto_e_flop:reset_l , ff_sre:goto_w_e_flop:reset_l , ff_sre:jsr_e_flop:reset_l , ff_sre:jsr_w_e_flop:reset_l , ff_sre:write_pc_e_flop:reset_l , ff_sre:ret_e_flop:reset_l , ff_sre:priv_powerdown_flop:reset_l , ff_sre:priv_reset_flop:reset_l , ff_sre:all_return_flop:reset_l , ff_sre_8:iu_inst_e_reg:reset_l , ff_sre_3:baload_e_reg:reset_l , ff_sre_3:bastore_e_reg:reset_l , ff_sre:all_load_c_flop:reset_l , ff_sre:iu_icu_flush_e_flop:reset_l , ff_sre_3:iu_dcu_flush_e_flop:reset_l , ff_sre:iu_zero_e_flop:reset_l , ff_sre:iu_special_e_ff:reset_l , ff_sre_4:iu_d_diag_e_reg:reset_l , ff_sre_4:iu_i_diag_e_reg:reset_l , ff_sre_8:opcode_1_op_e_reg:reset_l , ff_sre_8:opcode_1_op_c_reg:reset_l , ff_sre:ldst_half_word_e_flop:reset_l , ff_sre:ldst_half_word_c_flop:reset_l , ff_sre:ldst_word_e_flop:reset_l , ff_sre:ldst_word_c_flop:reset_l , ff_sre:iu_bypass_rs1_flop:reset_l , ff_sre:iu_bypass_rs2_flop:reset_l , ff_sre:nonnull_quick_reg:reset_l , ff_sre:monitorenter_e_flop:reset_l , ff_sre:monitorexit_e_flop:reset_l , ff_sre:carry_in_e_flop:reset_l , ff_sre:mul_e_flop:reset_l , ff_sre:div_e_flop:reset_l , ff_sre:rem_e_flop:reset_l , ff_sre:shift_dir_e_flop:reset_l , ff_sre:shift_sel_flop:reset_l , ff_sre:sign_e_flop:reset_l , ff_sre:shift_32_e_flop:reset_l , ff_sre:shift_64_e_flop:reset_l , ff_sre_6:shift_count_e1_flop:reset_l , ff_sre_2:bit_cvt_mux_sel_reg:reset_l , ff_sre_8:alu_out_mux_sel_raw_e_reg:reset_l , ff_sre:adder2_src1_mux_sel_reg:reset_l , ff_sre:adder2_src2_mux_sel_reg:reset_l , ff_sre_2:iu_data_mux_sel_reg:reset_l , ff_sre:iucmp_reg:reset_l , ff_sre:lcmp_reg:reset_l , ff_sre:first_cyc_reg:reset_l , ff_sre:second_cyc_reg:reset_l , ff_sre:first_gt_reg:reset_l , ff_sre:first_eq_reg:reset_l , ff_sre:first_lt_reg:reset_l , ff_sr:smu_access_reg:reset_l , ff_sre:load_store_c_reg:reset_l , ff_sre:data_brk1_c_reg:reset_l , ff_sre:data_brk2_c_reg:reset_l , ff_sr:load_buffer_fsm_reg:reset_l , ff_sre_21:reg_rd_mux_sel_raw_e_reg:reset_l , ff_sre_19:reg_wr_mux_sel_raw_e_reg:reset_l , ff_sre_2:ucode_rd_part_dcache_c_reg:reset_l , ff_sre_3:load_data_mux_sel_e_reg:reset_l , ff_sre_3:load_data_mux_sel_reg:reset_l , ff_sre:fpop_reg:reset_l , ff_sre_3:cmp_mux_sel_reg:reset_l , ff_sre_2:adder_src1_mux_sel_raw_ereg:reset_l , ff_sre:adder_src2_mux_sel_reg:reset_l , ff_sre:ucode_busy_e_reg:reset_l , ff_sre:ucode_busy_c_reg:reset_l , ff_sre_5:bit_mux_sel_reg:reset_l , ff_sre_5:cvt_mux_sel_reg:reset_l , ff_sre_5:shifter_src1_mux_sel_reg:reset_l , ff_sre_3:shifter_src2_mux_sel_reg:reset_l , ff_sre:shifter_word_sel_flop:reset_l , ff_sre_5:offset_mux_sel_reg:reset_l , mj_spare:spare1:reset_l , mj_spare:spare2:reset_l 
Connects up to:ex:ex_ctl:reset_l 
 reset_l : ex_dpath : input
Connects down to:ff_sr:flop_rs1_mux:reset_l , ff_sre_4:flop_rs1_bypass_sel:reset_l , ff_sr:flop_rs1_bypass_sel_4:reset_l , ff_sre_4:flop_rs2_bypass_sel:reset_l , ff_sr:flop_rs2_bypass_sel_4:reset_l , ff_sr:for_c_flop:reset_l 
Connects up to:ex:ex_dpath:reset_l 
 reset_l : ex_regs : input
Connects down to:mux2_30:vars_din_mux:sel , mux2_30:vars_din_mux:sel , mux2_29:oplim_din_mux:sel , mux2_29:oplim_din_mux:sel , mux2:psr_cac_mux:sel , mux2:psr_cac_mux:sel , mux2:psr_drt_mux:sel , mux2:psr_drt_mux:sel , ff_sre:psr_bm8_reg:reset_l , mux2:psr_ace_din_mux:sel , mux2:psr_ace_din_mux:sel , mux2:psr_gce_din_mux:sel , mux2:psr_gce_din_mux:sel , mux2:psr_fpe_din_mux:sel , mux2:psr_fpe_din_mux:sel , mux2:psr_dce_din_mux:sel , mux2:psr_dce_din_mux:sel , mux2:psr_ice_din_mux:sel , mux2:psr_ice_din_mux:sel , mux2:psr_aem_din_mux:sel , mux2:psr_aem_din_mux:sel , mux2:psr_dre_din_mux:sel , mux2:psr_dre_din_mux:sel , mux2:psr_fle_din_mux:sel , mux2:psr_fle_din_mux:sel , mux2:psr_su_din_mux:sel , mux2:psr_su_din_mux:sel , mux2:psr_ie_din_mux:sel , mux2:psr_ie_din_mux:sel , ff_sre_8:trapbase_tt_reg:reset_l , mux2_32:gc_config_din_mux:sel , mux2_32:gc_config_din_mux:sel , mux2:brk12c_halt_din_mux:sel , mux2:brk12c_halt_din_mux:sel , mux2_7:brk12c_brkm2_din_mux:sel , mux2_7:brk12c_brkm2_din_mux:sel , mux2_7:brk12c_brkm1_din_mux:sel , mux2_7:brk12c_brkm1_din_mux:sel , mux2:brk12c_subk2_din_mux:sel , mux2:brk12c_subk2_din_mux:sel , mux2_2:brk12c_srcbk2_din_mux:sel , mux2_2:brk12c_srcbk2_din_mux:sel , mux2:brk12c_brken2_din_mux:sel , mux2:brk12c_brken2_din_mux:sel , mux2:brk12c_subk1_din_mux:sel , mux2:brk12c_subk1_din_mux:sel , mux2_2:brk12c_srcbk1_din_mux:sel , mux2_2:brk12c_srcbk1_din_mux:sel , mux2:brk12c_brken1_din_mux:sel , mux2:brk12c_brken1_din_mux:sel , ff_sr_16:smu_addr_reg:reset_l 
Connects up to:ex:ex_regs:reset_l 
 reset_l : ff_sr : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l 
Connects up to:ex_ctl:ret_optop_update_flop:reset_l , ex_ctl:smu_access_reg:reset_l , ex_ctl:load_buffer_fsm_reg:reset_l , pipe_cntl:vld_w_reg:reset_l , pipe_cntl:hold_e_reg:reset_l , pipe_cntl:kill_dv_reg:reset_l , pipe_cntl:iu_perf_reg:reset_l , pipe_cntl:sc_sticky_reg:reset_l , pipe_cntl:fold_trapped_reg:reset_l , dcudp_cntl:diag_set_sel_reg:reset_l , dcudp_cntl:dcu_addr_c_31_reg:reset_l , dcudp_cntl:flush_set_sel_reg:reset_l , trap:async_err_reg:reset_l , trap:br_c_reg:reset_l , trap:trap_stat_reg:reset_l , ff_sr_2:ff_sr_0:reset_l , ff_sr_2:ff_sr_1:reset_l , ff_sr_3:ff_sr_0:reset_l , ff_sr_3:ff_sr_1:reset_l , ff_sr_3:ff_sr_2:reset_l , ff_sr_4:ff_sr_0:reset_l , ff_sr_4:ff_sr_1:reset_l , ff_sr_4:ff_sr_2:reset_l , ff_sr_4:ff_sr_3:reset_l , ff_sr_5:ff_sr_0:reset_l , ff_sr_5:ff_sr_1:reset_l , ff_sr_5:ff_sr_2:reset_l , ff_sr_5:ff_sr_3:reset_l , ff_sr_5:ff_sr_4:reset_l , ff_sr_6:ff_sr_0:reset_l , ff_sr_6:ff_sr_1:reset_l , ff_sr_6:ff_sr_2:reset_l , ff_sr_6:ff_sr_3:reset_l , ff_sr_6:ff_sr_4:reset_l , ff_sr_6:ff_sr_5:reset_l , ff_sr_7:ff_sr_0:reset_l , ff_sr_7:ff_sr_1:reset_l , ff_sr_7:ff_sr_2:reset_l , ff_sr_7:ff_sr_3:reset_l , ff_sr_7:ff_sr_4:reset_l , ff_sr_7:ff_sr_5:reset_l , ff_sr_7:ff_sr_6:reset_l , ff_sr_8:ff_sr_0:reset_l , ff_sr_8:ff_sr_1:reset_l , ff_sr_8:ff_sr_2:reset_l , ff_sr_8:ff_sr_3:reset_l , ff_sr_8:ff_sr_4:reset_l , ff_sr_8:ff_sr_5:reset_l , ff_sr_8:ff_sr_6:reset_l , ff_sr_8:ff_sr_7:reset_l , ff_sr_9:ff_sr_0:reset_l , ff_sr_9:ff_sr_1:reset_l , ff_sr_9:ff_sr_2:reset_l , ff_sr_9:ff_sr_3:reset_l , ff_sr_9:ff_sr_4:reset_l , ff_sr_9:ff_sr_5:reset_l , ff_sr_9:ff_sr_6:reset_l , ff_sr_9:ff_sr_7:reset_l , ff_sr_9:ff_sr_8:reset_l , ff_sr_10:ff_sr_0:reset_l , ff_sr_10:ff_sr_1:reset_l , ff_sr_10:ff_sr_2:reset_l , ff_sr_10:ff_sr_3:reset_l , ff_sr_10:ff_sr_4:reset_l , ff_sr_10:ff_sr_5:reset_l , ff_sr_10:ff_sr_6:reset_l , ff_sr_10:ff_sr_7:reset_l , ff_sr_10:ff_sr_8:reset_l , ff_sr_10:ff_sr_9:reset_l , ff_sr_11:ff_sr_0:reset_l , ff_sr_11:ff_sr_1:reset_l , ff_sr_11:ff_sr_2:reset_l , ff_sr_11:ff_sr_3:reset_l , ff_sr_11:ff_sr_4:reset_l , ff_sr_11:ff_sr_5:reset_l , ff_sr_11:ff_sr_6:reset_l , ff_sr_11:ff_sr_7:reset_l , ff_sr_11:ff_sr_8:reset_l , ff_sr_11:ff_sr_9:reset_l , ff_sr_11:ff_sr_10:reset_l , ff_sr_12:ff_sr_0:reset_l , ff_sr_12:ff_sr_1:reset_l , ff_sr_12:ff_sr_2:reset_l , ff_sr_12:ff_sr_3:reset_l , ff_sr_12:ff_sr_4:reset_l , ff_sr_12:ff_sr_5:reset_l , ff_sr_12:ff_sr_6:reset_l , ff_sr_12:ff_sr_7:reset_l , ff_sr_12:ff_sr_8:reset_l , ff_sr_12:ff_sr_9:reset_l , ff_sr_12:ff_sr_10:reset_l , ff_sr_12:ff_sr_11:reset_l , ff_sr_13:ff_sr_0:reset_l , ff_sr_13:ff_sr_1:reset_l , ff_sr_13:ff_sr_2:reset_l , ff_sr_13:ff_sr_3:reset_l , ff_sr_13:ff_sr_4:reset_l , ff_sr_13:ff_sr_5:reset_l , ff_sr_13:ff_sr_6:reset_l , ff_sr_13:ff_sr_7:reset_l , ff_sr_13:ff_sr_8:reset_l , ff_sr_13:ff_sr_9:reset_l , ff_sr_13:ff_sr_10:reset_l , ff_sr_13:ff_sr_11:reset_l , ff_sr_13:ff_sr_12:reset_l , ff_sr_14:ff_sr_0:reset_l , ff_sr_14:ff_sr_1:reset_l , ff_sr_14:ff_sr_2:reset_l , ff_sr_14:ff_sr_3:reset_l , ff_sr_14:ff_sr_4:reset_l , ff_sr_14:ff_sr_5:reset_l , ff_sr_14:ff_sr_6:reset_l , ff_sr_14:ff_sr_7:reset_l , ff_sr_14:ff_sr_8:reset_l , ff_sr_14:ff_sr_9:reset_l , ff_sr_14:ff_sr_10:reset_l , ff_sr_14:ff_sr_11:reset_l , ff_sr_14:ff_sr_12:reset_l , ff_sr_14:ff_sr_13:reset_l , ff_sr_15:ff_sr_0:reset_l , ff_sr_15:ff_sr_1:reset_l , ff_sr_15:ff_sr_2:reset_l , ff_sr_15:ff_sr_3:reset_l , ff_sr_15:ff_sr_4:reset_l , ff_sr_15:ff_sr_5:reset_l , ff_sr_15:ff_sr_6:reset_l , ff_sr_15:ff_sr_7:reset_l , ff_sr_15:ff_sr_8:reset_l , ff_sr_15:ff_sr_9:reset_l , ff_sr_15:ff_sr_10:reset_l , ff_sr_15:ff_sr_11:reset_l , ff_sr_15:ff_sr_12:reset_l , ff_sr_15:ff_sr_13:reset_l , ff_sr_15:ff_sr_14:reset_l , ff_sr_16:ff_sr_0:reset_l , ff_sr_16:ff_sr_1:reset_l , ff_sr_16:ff_sr_2:reset_l , ff_sr_16:ff_sr_3:reset_l , ff_sr_16:ff_sr_4:reset_l , ff_sr_16:ff_sr_5:reset_l , ff_sr_16:ff_sr_6:reset_l , ff_sr_16:ff_sr_7:reset_l , ff_sr_16:ff_sr_8:reset_l , ff_sr_16:ff_sr_9:reset_l , ff_sr_16:ff_sr_10:reset_l , ff_sr_16:ff_sr_11:reset_l , ff_sr_16:ff_sr_12:reset_l , ff_sr_16:ff_sr_13:reset_l , ff_sr_16:ff_sr_14:reset_l , ff_sr_16:ff_sr_15:reset_l , ff_sr_17:ff_sr_0:reset_l , ff_sr_17:ff_sr_1:reset_l , ff_sr_17:ff_sr_2:reset_l , ff_sr_17:ff_sr_3:reset_l , ff_sr_17:ff_sr_4:reset_l , ff_sr_17:ff_sr_5:reset_l , ff_sr_17:ff_sr_6:reset_l , ff_sr_17:ff_sr_7:reset_l , ff_sr_17:ff_sr_8:reset_l , ff_sr_17:ff_sr_9:reset_l , ff_sr_17:ff_sr_10:reset_l , ff_sr_17:ff_sr_11:reset_l , ff_sr_17:ff_sr_12:reset_l , ff_sr_17:ff_sr_13:reset_l , ff_sr_17:ff_sr_14:reset_l , ff_sr_17:ff_sr_15:reset_l , ff_sr_17:ff_sr_16:reset_l , ff_sr_18:ff_sr_0:reset_l , ff_sr_18:ff_sr_1:reset_l , ff_sr_18:ff_sr_2:reset_l , ff_sr_18:ff_sr_3:reset_l , ff_sr_18:ff_sr_4:reset_l , ff_sr_18:ff_sr_5:reset_l , ff_sr_18:ff_sr_6:reset_l , ff_sr_18:ff_sr_7:reset_l , ff_sr_18:ff_sr_8:reset_l , ff_sr_18:ff_sr_9:reset_l , ff_sr_18:ff_sr_10:reset_l , ff_sr_18:ff_sr_11:reset_l , ff_sr_18:ff_sr_12:reset_l , ff_sr_18:ff_sr_13:reset_l , ff_sr_18:ff_sr_14:reset_l , ff_sr_18:ff_sr_15:reset_l , ff_sr_18:ff_sr_16:reset_l , ff_sr_18:ff_sr_17:reset_l , ff_sr_19:ff_sr_0:reset_l , ff_sr_19:ff_sr_1:reset_l , ff_sr_19:ff_sr_2:reset_l , ff_sr_19:ff_sr_3:reset_l , ff_sr_19:ff_sr_4:reset_l , ff_sr_19:ff_sr_5:reset_l , ff_sr_19:ff_sr_6:reset_l , ff_sr_19:ff_sr_7:reset_l , ff_sr_19:ff_sr_8:reset_l , ff_sr_19:ff_sr_9:reset_l , ff_sr_19:ff_sr_10:reset_l , ff_sr_19:ff_sr_11:reset_l , ff_sr_19:ff_sr_12:reset_l , ff_sr_19:ff_sr_13:reset_l , ff_sr_19:ff_sr_14:reset_l , ff_sr_19:ff_sr_15:reset_l , ff_sr_19:ff_sr_16:reset_l , ff_sr_19:ff_sr_17:reset_l , ff_sr_19:ff_sr_18:reset_l , ff_sr_20:ff_sr_0:reset_l , ff_sr_20:ff_sr_1:reset_l , ff_sr_20:ff_sr_2:reset_l , ff_sr_20:ff_sr_3:reset_l , ff_sr_20:ff_sr_4:reset_l , ff_sr_20:ff_sr_5:reset_l , ff_sr_20:ff_sr_6:reset_l , ff_sr_20:ff_sr_7:reset_l , ff_sr_20:ff_sr_8:reset_l , ff_sr_20:ff_sr_9:reset_l , ff_sr_20:ff_sr_10:reset_l , ff_sr_20:ff_sr_11:reset_l , ff_sr_20:ff_sr_12:reset_l , ff_sr_20:ff_sr_13:reset_l , ff_sr_20:ff_sr_14:reset_l , ff_sr_20:ff_sr_15:reset_l , ff_sr_20:ff_sr_16:reset_l , ff_sr_20:ff_sr_17:reset_l , ff_sr_20:ff_sr_18:reset_l , ff_sr_20:ff_sr_19:reset_l , ff_sr_21:ff_sr_0:reset_l , ff_sr_21:ff_sr_1:reset_l , ff_sr_21:ff_sr_2:reset_l , ff_sr_21:ff_sr_3:reset_l , ff_sr_21:ff_sr_4:reset_l , ff_sr_21:ff_sr_5:reset_l , ff_sr_21:ff_sr_6:reset_l , ff_sr_21:ff_sr_7:reset_l , ff_sr_21:ff_sr_8:reset_l , ff_sr_21:ff_sr_9:reset_l , ff_sr_21:ff_sr_10:reset_l , ff_sr_21:ff_sr_11:reset_l , ff_sr_21:ff_sr_12:reset_l , ff_sr_21:ff_sr_13:reset_l , ff_sr_21:ff_sr_14:reset_l , ff_sr_21:ff_sr_15:reset_l , ff_sr_21:ff_sr_16:reset_l , ff_sr_21:ff_sr_17:reset_l , ff_sr_21:ff_sr_18:reset_l , ff_sr_21:ff_sr_19:reset_l , ff_sr_21:ff_sr_20:reset_l , ff_sr_22:ff_sr_0:reset_l , ff_sr_22:ff_sr_1:reset_l , ff_sr_22:ff_sr_2:reset_l , ff_sr_22:ff_sr_3:reset_l , ff_sr_22:ff_sr_4:reset_l , ff_sr_22:ff_sr_5:reset_l , ff_sr_22:ff_sr_6:reset_l , ff_sr_22:ff_sr_7:reset_l , ff_sr_22:ff_sr_8:reset_l , ff_sr_22:ff_sr_9:reset_l , ff_sr_22:ff_sr_10:reset_l , ff_sr_22:ff_sr_11:reset_l , ff_sr_22:ff_sr_12:reset_l , ff_sr_22:ff_sr_13:reset_l , ff_sr_22:ff_sr_14:reset_l , ff_sr_22:ff_sr_15:reset_l , ff_sr_22:ff_sr_16:reset_l , ff_sr_22:ff_sr_17:reset_l , ff_sr_22:ff_sr_18:reset_l , ff_sr_22:ff_sr_19:reset_l , ff_sr_22:ff_sr_20:reset_l , ff_sr_22:ff_sr_21:reset_l , ff_sr_23:ff_sr_0:reset_l , ff_sr_23:ff_sr_1:reset_l , ff_sr_23:ff_sr_2:reset_l , ff_sr_23:ff_sr_3:reset_l , ff_sr_23:ff_sr_4:reset_l , ff_sr_23:ff_sr_5:reset_l , ff_sr_23:ff_sr_6:reset_l , ff_sr_23:ff_sr_7:reset_l , ff_sr_23:ff_sr_8:reset_l , ff_sr_23:ff_sr_9:reset_l , ff_sr_23:ff_sr_10:reset_l , ff_sr_23:ff_sr_11:reset_l , ff_sr_23:ff_sr_12:reset_l , ff_sr_23:ff_sr_13:reset_l , ff_sr_23:ff_sr_14:reset_l , ff_sr_23:ff_sr_15:reset_l , ff_sr_23:ff_sr_16:reset_l , ff_sr_23:ff_sr_17:reset_l , ff_sr_23:ff_sr_18:reset_l , ff_sr_23:ff_sr_19:reset_l , ff_sr_23:ff_sr_20:reset_l , ff_sr_23:ff_sr_21:reset_l , ff_sr_23:ff_sr_22:reset_l , ff_sr_24:ff_sr_0:reset_l , ff_sr_24:ff_sr_1:reset_l , ff_sr_24:ff_sr_2:reset_l , ff_sr_24:ff_sr_3:reset_l , ff_sr_24:ff_sr_4:reset_l , ff_sr_24:ff_sr_5:reset_l , ff_sr_24:ff_sr_6:reset_l , ff_sr_24:ff_sr_7:reset_l , ff_sr_24:ff_sr_8:reset_l , ff_sr_24:ff_sr_9:reset_l , ff_sr_24:ff_sr_10:reset_l , ff_sr_24:ff_sr_11:reset_l , ff_sr_24:ff_sr_12:reset_l , ff_sr_24:ff_sr_13:reset_l , ff_sr_24:ff_sr_14:reset_l , ff_sr_24:ff_sr_15:reset_l , ff_sr_24:ff_sr_16:reset_l , ff_sr_24:ff_sr_17:reset_l , ff_sr_24:ff_sr_18:reset_l , ff_sr_24:ff_sr_19:reset_l , ff_sr_24:ff_sr_20:reset_l , ff_sr_24:ff_sr_21:reset_l , ff_sr_24:ff_sr_22:reset_l , ff_sr_24:ff_sr_23:reset_l , ff_sr_25:ff_sr_0:reset_l , ff_sr_25:ff_sr_1:reset_l , ff_sr_25:ff_sr_2:reset_l , ff_sr_25:ff_sr_3:reset_l , ff_sr_25:ff_sr_4:reset_l , ff_sr_25:ff_sr_5:reset_l , ff_sr_25:ff_sr_6:reset_l , ff_sr_25:ff_sr_7:reset_l , ff_sr_25:ff_sr_8:reset_l , ff_sr_25:ff_sr_9:reset_l , ff_sr_25:ff_sr_10:reset_l , ff_sr_25:ff_sr_11:reset_l , ff_sr_25:ff_sr_12:reset_l , ff_sr_25:ff_sr_13:reset_l , ff_sr_25:ff_sr_14:reset_l , ff_sr_25:ff_sr_15:reset_l , ff_sr_25:ff_sr_16:reset_l , ff_sr_25:ff_sr_17:reset_l , ff_sr_25:ff_sr_18:reset_l , ff_sr_25:ff_sr_19:reset_l , ff_sr_25:ff_sr_20:reset_l , ff_sr_25:ff_sr_21:reset_l , ff_sr_25:ff_sr_22:reset_l , ff_sr_25:ff_sr_23:reset_l , ff_sr_25:ff_sr_24:reset_l , ff_sr_26:ff_sr_0:reset_l , ff_sr_26:ff_sr_1:reset_l , ff_sr_26:ff_sr_2:reset_l , ff_sr_26:ff_sr_3:reset_l , ff_sr_26:ff_sr_4:reset_l , ff_sr_26:ff_sr_5:reset_l , ff_sr_26:ff_sr_6:reset_l , ff_sr_26:ff_sr_7:reset_l , ff_sr_26:ff_sr_8:reset_l , ff_sr_26:ff_sr_9:reset_l , ff_sr_26:ff_sr_10:reset_l , ff_sr_26:ff_sr_11:reset_l , ff_sr_26:ff_sr_12:reset_l , ff_sr_26:ff_sr_13:reset_l , ff_sr_26:ff_sr_14:reset_l , ff_sr_26:ff_sr_15:reset_l , ff_sr_26:ff_sr_16:reset_l , ff_sr_26:ff_sr_17:reset_l , ff_sr_26:ff_sr_18:reset_l , ff_sr_26:ff_sr_19:reset_l , ff_sr_26:ff_sr_20:reset_l , ff_sr_26:ff_sr_21:reset_l , ff_sr_26:ff_sr_22:reset_l , ff_sr_26:ff_sr_23:reset_l , ff_sr_26:ff_sr_24:reset_l , ff_sr_26:ff_sr_25:reset_l , ff_sr_27:ff_sr_0:reset_l , ff_sr_27:ff_sr_1:reset_l , ff_sr_27:ff_sr_2:reset_l , ff_sr_27:ff_sr_3:reset_l , ff_sr_27:ff_sr_4:reset_l , ff_sr_27:ff_sr_5:reset_l , ff_sr_27:ff_sr_6:reset_l , ff_sr_27:ff_sr_7:reset_l , ff_sr_27:ff_sr_8:reset_l , ff_sr_27:ff_sr_9:reset_l , ff_sr_27:ff_sr_10:reset_l , ff_sr_27:ff_sr_11:reset_l , ff_sr_27:ff_sr_12:reset_l , ff_sr_27:ff_sr_13:reset_l , ff_sr_27:ff_sr_14:reset_l , ff_sr_27:ff_sr_15:reset_l , ff_sr_27:ff_sr_16:reset_l , ff_sr_27:ff_sr_17:reset_l , ff_sr_27:ff_sr_18:reset_l , ff_sr_27:ff_sr_19:reset_l , ff_sr_27:ff_sr_20:reset_l , ff_sr_27:ff_sr_21:reset_l , ff_sr_27:ff_sr_22:reset_l , ff_sr_27:ff_sr_23:reset_l , ff_sr_27:ff_sr_24:reset_l , ff_sr_27:ff_sr_25:reset_l , ff_sr_27:ff_sr_26:reset_l , ff_sr_28:ff_sr_0:reset_l , ff_sr_28:ff_sr_1:reset_l , ff_sr_28:ff_sr_2:reset_l , ff_sr_28:ff_sr_3:reset_l , ff_sr_28:ff_sr_4:reset_l , ff_sr_28:ff_sr_5:reset_l , ff_sr_28:ff_sr_6:reset_l , ff_sr_28:ff_sr_7:reset_l , ff_sr_28:ff_sr_8:reset_l , ff_sr_28:ff_sr_9:reset_l , ff_sr_28:ff_sr_10:reset_l , ff_sr_28:ff_sr_11:reset_l , ff_sr_28:ff_sr_12:reset_l , ff_sr_28:ff_sr_13:reset_l , ff_sr_28:ff_sr_14:reset_l , ff_sr_28:ff_sr_15:reset_l , ff_sr_28:ff_sr_16:reset_l , ff_sr_28:ff_sr_17:reset_l , ff_sr_28:ff_sr_18:reset_l , ff_sr_28:ff_sr_19:reset_l , ff_sr_28:ff_sr_20:reset_l , ff_sr_28:ff_sr_21:reset_l , ff_sr_28:ff_sr_22:reset_l , ff_sr_28:ff_sr_23:reset_l , ff_sr_28:ff_sr_24:reset_l , ff_sr_28:ff_sr_25:reset_l , ff_sr_28:ff_sr_26:reset_l , ff_sr_28:ff_sr_27:reset_l , ff_sr_29:ff_sr_0:reset_l , ff_sr_29:ff_sr_1:reset_l , ff_sr_29:ff_sr_2:reset_l , ff_sr_29:ff_sr_3:reset_l , ff_sr_29:ff_sr_4:reset_l , ff_sr_29:ff_sr_5:reset_l , ff_sr_29:ff_sr_6:reset_l , ff_sr_29:ff_sr_7:reset_l , ff_sr_29:ff_sr_8:reset_l , ff_sr_29:ff_sr_9:reset_l , ff_sr_29:ff_sr_10:reset_l , ff_sr_29:ff_sr_11:reset_l , ff_sr_29:ff_sr_12:reset_l , ff_sr_29:ff_sr_13:reset_l , ff_sr_29:ff_sr_14:reset_l , ff_sr_29:ff_sr_15:reset_l , ff_sr_29:ff_sr_16:reset_l , ff_sr_29:ff_sr_17:reset_l , ff_sr_29:ff_sr_18:reset_l , ff_sr_29:ff_sr_19:reset_l , ff_sr_29:ff_sr_20:reset_l , ff_sr_29:ff_sr_21:reset_l , ff_sr_29:ff_sr_22:reset_l , ff_sr_29:ff_sr_23:reset_l , ff_sr_29:ff_sr_24:reset_l , ff_sr_29:ff_sr_25:reset_l , ff_sr_29:ff_sr_26:reset_l , ff_sr_29:ff_sr_27:reset_l , ff_sr_29:ff_sr_28:reset_l , imdr_ctrl:ff_ss_0:reset_l , imdr_ctrl:ff_ss_1:reset_l , ff_sr_30:ff_sr_0:reset_l , ff_sr_30:ff_sr_1:reset_l , ff_sr_30:ff_sr_2:reset_l , ff_sr_30:ff_sr_3:reset_l , ff_sr_30:ff_sr_4:reset_l , ff_sr_30:ff_sr_5:reset_l , ff_sr_30:ff_sr_6:reset_l , ff_sr_30:ff_sr_7:reset_l , ff_sr_30:ff_sr_8:reset_l , ff_sr_30:ff_sr_9:reset_l , ff_sr_30:ff_sr_10:reset_l , ff_sr_30:ff_sr_11:reset_l , ff_sr_30:ff_sr_12:reset_l , ff_sr_30:ff_sr_13:reset_l , ff_sr_30:ff_sr_14:reset_l , ff_sr_30:ff_sr_15:reset_l , ff_sr_30:ff_sr_16:reset_l , ff_sr_30:ff_sr_17:reset_l , ff_sr_30:ff_sr_18:reset_l , ff_sr_30:ff_sr_19:reset_l , ff_sr_30:ff_sr_20:reset_l , ff_sr_30:ff_sr_21:reset_l , ff_sr_30:ff_sr_22:reset_l , ff_sr_30:ff_sr_23:reset_l , ff_sr_30:ff_sr_24:reset_l , ff_sr_30:ff_sr_25:reset_l , ff_sr_30:ff_sr_26:reset_l , ff_sr_30:ff_sr_27:reset_l , ff_sr_30:ff_sr_28:reset_l , ff_sr_30:ff_sr_29:reset_l , ff_sr_31:ff_sr_0:reset_l , ff_sr_31:ff_sr_1:reset_l , ff_sr_31:ff_sr_2:reset_l , ff_sr_31:ff_sr_3:reset_l , ff_sr_31:ff_sr_4:reset_l , ff_sr_31:ff_sr_5:reset_l , ff_sr_31:ff_sr_6:reset_l , ff_sr_31:ff_sr_7:reset_l , ff_sr_31:ff_sr_8:reset_l , ff_sr_31:ff_sr_9:reset_l , ff_sr_31:ff_sr_10:reset_l , ff_sr_31:ff_sr_11:reset_l , ff_sr_31:ff_sr_12:reset_l , ff_sr_31:ff_sr_13:reset_l , ff_sr_31:ff_sr_14:reset_l , ff_sr_31:ff_sr_15:reset_l , ff_sr_31:ff_sr_16:reset_l , ff_sr_31:ff_sr_17:reset_l , ff_sr_31:ff_sr_18:reset_l , ff_sr_31:ff_sr_19:reset_l , ff_sr_31:ff_sr_20:reset_l , ff_sr_31:ff_sr_21:reset_l , ff_sr_31:ff_sr_22:reset_l , ff_sr_31:ff_sr_23:reset_l , ff_sr_31:ff_sr_24:reset_l , ff_sr_31:ff_sr_25:reset_l , ff_sr_31:ff_sr_26:reset_l , ff_sr_31:ff_sr_27:reset_l , ff_sr_31:ff_sr_28:reset_l , ff_sr_31:ff_sr_29:reset_l , ff_sr_31:ff_sr_30:reset_l , ff_sr_32:ff_sr_0:reset_l , ff_sr_32:ff_sr_1:reset_l , ff_sr_32:ff_sr_2:reset_l , ff_sr_32:ff_sr_3:reset_l , ff_sr_32:ff_sr_4:reset_l , ff_sr_32:ff_sr_5:reset_l , ff_sr_32:ff_sr_6:reset_l , ff_sr_32:ff_sr_7:reset_l , ff_sr_32:ff_sr_8:reset_l , ff_sr_32:ff_sr_9:reset_l , ff_sr_32:ff_sr_10:reset_l , ff_sr_32:ff_sr_11:reset_l , ff_sr_32:ff_sr_12:reset_l , ff_sr_32:ff_sr_13:reset_l , ff_sr_32:ff_sr_14:reset_l , ff_sr_32:ff_sr_15:reset_l , ff_sr_32:ff_sr_16:reset_l , ff_sr_32:ff_sr_17:reset_l , ff_sr_32:ff_sr_18:reset_l , ff_sr_32:ff_sr_19:reset_l , ff_sr_32:ff_sr_20:reset_l , ff_sr_32:ff_sr_21:reset_l , ff_sr_32:ff_sr_22:reset_l , ff_sr_32:ff_sr_23:reset_l , ff_sr_32:ff_sr_24:reset_l , ff_sr_32:ff_sr_25:reset_l , ff_sr_32:ff_sr_26:reset_l , ff_sr_32:ff_sr_27:reset_l , ff_sr_32:ff_sr_28:reset_l , ff_sr_32:ff_sr_29:reset_l , ff_sr_32:ff_sr_30:reset_l , ff_sr_32:ff_sr_31:reset_l , smu_ctl:spill_flop:reset_l , smu_ctl:fill_flop:reset_l , smu_ctl:ovr_flw_flop:reset_l , smu_ctl:und_flw_flop:reset_l , smu_ctl:flush_flop:reset_l , smu_ctl:int_flop:reset_l , smu_ctl:load_w_flop:reset_l , smu_ctl:store_w_flop:reset_l , smu_ctl:delay_flop1:reset_l , smu_ctl:delay_flop2:reset_l , smu_ctl:iu_smiss_flop:reset_l , smu_ctl:squash_flop1:reset_l , smu_ctl:squash_flop2:reset_l , smu_ctl:squash_flop3:reset_l , smu_ctl:zero_flop:reset_l , smu_ctl:idle_flop:reset_l , smu_ctl:smu_prty_flop:reset_l , smu_ctl:squash_flop:reset_l , smu_ctl:six_state_reg:reset_l , dc_dec:squash_inst_reg:reset_l , dc_dec:smu_stall_store_reg:reset_l , dc_dec:miss_stall_vld_reg:reset_l , dc_dec:smu_miss_stall_vld_reg:reset_l , dc_dec:smu_na_st_miss_reg:reset_l , dc_dec:smu_na_st_miss_c2_reg:reset_l , dc_dec:iu_reciculating_reg:reset_l , dc_dec:smu_reciculating_reg:reset_l , dc_dec:iu_pending_reg:reset_l , dc_dec:smu_pending_reg:reset_l , dc_dec:miss_sustain_reg:reset_l , dc_dec:fill_cyc_d1reg:reset_l , dc_dec:pwrdown_reg:reset_l , ibuf_ctl:squash_vld_reg:reset_l , rcu_ctl:flop_scache_hit:reset_l , rcu_ctl:flop_data_we_w:reset_l , rcu_ctl:flop_scache_wr_miss:reset_l , rcu_ctl:flop_global_we_w:reset_l , rcu_ctl:flop_mult_cyc_st:reset_l , rcu_ctl:flop_fc_w:reset_l , ex_dpath:flop_rs1_mux:reset_l , ex_dpath:flop_rs1_bypass_sel_4:reset_l , ex_dpath:flop_rs2_bypass_sel_4:reset_l , ex_dpath:for_c_flop:reset_l , wrbuf_cntl:repl_state_reg0:reset_l , wrbuf_cntl:repl_state_reg1:reset_l 
 reset_l : ff_sre : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:reset_l 
Connects up to:ifu:flop_gr_1:reset_l , ifu:flop_gr_2:reset_l , ifu:flop_gr_3:reset_l , ifu:flop_gr_4:reset_l , ifu:flop_gr_5:reset_l , ifu:flop_gr_6:reset_l , ifu:flop_gr_7:reset_l , ifu:flop_gr_8:reset_l , ifu:flop_gr_9:reset_l , ifu:flop_fold:reset_l , ifu:flop_no_fold:reset_l , ifu:flop_valid_rs1:reset_l , ifu:flop_help_rs1:reset_l , ifu:flop_lv_rs1:reset_l , ifu:flop_lv_acc_rs1:reset_l , ifu:flop_rev_ops:reset_l , ifu:flop_st_op:reset_l , ifu:flop_optop:reset_l , ifu:flop_vld_rs2:reset_l , ifu:flop_lv_rs2:reset_l , ifu:flop_lvars_acc_rs2:reset_l , ifu:flop_vld_op_rcu:reset_l , ifu:flop_vld_op_ucode:reset_l , ifu:flop_vld_op_gen:reset_l , ifu:flop_vld_rsd:reset_l , ifu:flop_drty_inst:reset_l , ifu:flop_putfield:reset_l , ex_ctl:data_brk1_c_reg:pj_resume , ex_ctl:data_brk2_c_reg:pj_resume , ex_ctl:wr_optop_e_flop:reset_l , ex_ctl:ifeq_e_flop:reset_l , ex_ctl:if_icmpeq_e_flop:reset_l , ex_ctl:if_acmpeq_e_flop:reset_l , ex_ctl:ifge_e_flop:reset_l , ex_ctl:if_icmpge_e_flop:reset_l , ex_ctl:ifle_e_flop:reset_l , ex_ctl:if_icmple_e_flop:reset_l , ex_ctl:ifnull_e_flop:reset_l , ex_ctl:ifne_e_flop:reset_l , ex_ctl:if_icmpne_e_flop:reset_l , ex_ctl:if_acmpne_e_flop:reset_l , ex_ctl:ifnonnull_e_flop:reset_l , ex_ctl:ifgt_e_flop:reset_l , ex_ctl:if_icmpgt_e_flop:reset_l , ex_ctl:iflt_e_flop:reset_l , ex_ctl:if_icmplt_e_flop:reset_l , ex_ctl:goto_e_flop:reset_l , ex_ctl:goto_w_e_flop:reset_l , ex_ctl:jsr_e_flop:reset_l , ex_ctl:jsr_w_e_flop:reset_l , ex_ctl:write_pc_e_flop:reset_l , ex_ctl:ret_e_flop:reset_l , ex_ctl:priv_powerdown_flop:reset_l , ex_ctl:priv_reset_flop:reset_l , ex_ctl:all_return_flop:reset_l , ex_ctl:all_load_c_flop:reset_l , ex_ctl:iu_icu_flush_e_flop:reset_l , ex_ctl:iu_zero_e_flop:reset_l , ex_ctl:iu_special_e_ff:reset_l , ex_ctl:ldst_half_word_e_flop:reset_l , ex_ctl:ldst_half_word_c_flop:reset_l , ex_ctl:ldst_word_e_flop:reset_l , ex_ctl:ldst_word_c_flop:reset_l , ex_ctl:iu_bypass_rs1_flop:reset_l , ex_ctl:iu_bypass_rs2_flop:reset_l , ex_ctl:nonnull_quick_reg:reset_l , ex_ctl:monitorenter_e_flop:reset_l , ex_ctl:monitorexit_e_flop:reset_l , ex_ctl:carry_in_e_flop:reset_l , ex_ctl:mul_e_flop:reset_l , ex_ctl:div_e_flop:reset_l , ex_ctl:rem_e_flop:reset_l , ex_ctl:shift_dir_e_flop:reset_l , ex_ctl:shift_sel_flop:reset_l , ex_ctl:sign_e_flop:reset_l , ex_ctl:shift_32_e_flop:reset_l , ex_ctl:shift_64_e_flop:reset_l , ex_ctl:adder2_src1_mux_sel_reg:reset_l , ex_ctl:adder2_src2_mux_sel_reg:reset_l , ex_ctl:iucmp_reg:reset_l , ex_ctl:lcmp_reg:reset_l , ex_ctl:first_cyc_reg:reset_l , ex_ctl:second_cyc_reg:reset_l , ex_ctl:first_gt_reg:reset_l , ex_ctl:first_eq_reg:reset_l , ex_ctl:first_lt_reg:reset_l , ex_ctl:load_store_c_reg:reset_l , ex_ctl:data_brk1_c_reg:reset_l , ex_ctl:data_brk2_c_reg:reset_l , ex_ctl:fpop_reg:reset_l , ex_ctl:adder_src2_mux_sel_reg:reset_l , ex_ctl:ucode_busy_e_reg:reset_l , ex_ctl:ucode_busy_c_reg:reset_l , ex_ctl:shifter_word_sel_flop:reset_l , ucode_seq:last_reg:reg_clear_l , ucode_seq:abt_rdwt_reg:reg_clear_l , ucode_seq:abt_cur_reg:reg_clear_l , ucode_seq:ary_null_reg:reg_clear_l , ucode_seq:ary_ovf_reg:reg_clear_l , ucode_seq:ptr_un_eq_reg:reg_clear_l , ucode_seq:ptr_gc_notify:reg_clear_l , ucode_monitor:reset_l_minus_1:reset_l , ucode_monitor:reset_l_minus_2:reset_l , ucode_monitor:reset_l_minus_3:reset_l , ucode_monitor:invoke_e_flop:reset_l , pipe_cntl:vld_e_reg:reset_l , pipe_cntl:vld_e_v1_reg:reset_l , pipe_cntl:vld_c_reg:reset_l , pipe_cntl:flop_bypass_rs1_hit:reset_l , pipe_cntl:flop_bypass_rs2_hit:reset_l , pipe_cntl:ucode_done_reg:reset_l , pipe_cntl:fold_e_reg:reset_l , pipe_cntl:fold_c_reg:reset_l , pipe_cntl:fold_sc_reg:reset_l , ff_sre_2:ff_sre_0:reset_l , ff_sre_2:ff_sre_1:reset_l , ff_sre_3:ff_sre_0:reset_l , ff_sre_3:ff_sre_1:reset_l , ff_sre_3:ff_sre_2:reset_l , ff_sre_4:ff_sre_0:reset_l , ff_sre_4:ff_sre_1:reset_l , ff_sre_4:ff_sre_2:reset_l , ff_sre_4:ff_sre_3:reset_l , ff_sre_5:ff_sre_0:reset_l , ff_sre_5:ff_sre_1:reset_l , ff_sre_5:ff_sre_2:reset_l , ff_sre_5:ff_sre_3:reset_l , ff_sre_5:ff_sre_4:reset_l , ff_sre_6:ff_sre_0:reset_l , ff_sre_6:ff_sre_1:reset_l , ff_sre_6:ff_sre_2:reset_l , ff_sre_6:ff_sre_3:reset_l , ff_sre_6:ff_sre_4:reset_l , ff_sre_6:ff_sre_5:reset_l , ff_sre_7:ff_sre_0:reset_l , ff_sre_7:ff_sre_1:reset_l , ff_sre_7:ff_sre_2:reset_l , ff_sre_7:ff_sre_3:reset_l , ff_sre_7:ff_sre_4:reset_l , ff_sre_7:ff_sre_5:reset_l , ff_sre_7:ff_sre_6:reset_l , ff_sre_8:ff_sre_0:reset_l , ff_sre_8:ff_sre_1:reset_l , ff_sre_8:ff_sre_2:reset_l , ff_sre_8:ff_sre_3:reset_l , ff_sre_8:ff_sre_4:reset_l , ff_sre_8:ff_sre_5:reset_l , ff_sre_8:ff_sre_6:reset_l , ff_sre_8:ff_sre_7:reset_l , ff_sre_9:ff_sre_0:reset_l , ff_sre_9:ff_sre_1:reset_l , ff_sre_9:ff_sre_2:reset_l , ff_sre_9:ff_sre_3:reset_l , ff_sre_9:ff_sre_4:reset_l , ff_sre_9:ff_sre_5:reset_l , ff_sre_9:ff_sre_6:reset_l , ff_sre_9:ff_sre_7:reset_l , ff_sre_9:ff_sre_8:reset_l , dcudp_cntl:tag_set_reg:reset_l , trap:inst_brk1_c_reg:pj_resume , trap:inst_brk2_c_reg:pj_resume , trap:irl_r_reg:reset_l , trap:irl_e_reg:reset_l , trap:irl_c_reg:reset_l , trap:nmi_r_reg:reset_l , trap:nmi_e_reg:reset_l , trap:nmi_c_reg:reset_l , trap:inst_brk1_e_reg:reset_l , trap:inst_brk2_e_reg:reset_l , trap:inst_brk1_c_reg:reset_l , trap:inst_brk2_c_reg:reset_l , trap:first_cyc_c_reg:reset_l , trap:imem_e_reg:reset_l , trap:imem_c_reg:reset_l , trap:ill_e_reg:reset_l , trap:ill_c_reg:reset_l , trap:priv_e_reg:reset_l , trap:priv_c_reg:reset_l , trap:fpu_e_reg:reset_l , trap:fpu_c_reg:reset_l , trap:emul_op_e_reg:reset_l , trap:emul_op_c_reg:reset_l , trap:soft_e_reg:reset_l , trap:soft_c_reg:reset_l , trap:zero_c_reg:reset_l , trap:vm_err_c_reg:reset_l , trap:null_ptr_c_reg:reset_l , trap:trap_vld_e_reg:reset_l , trap:trap_vld_c_reg:reset_l , trap:iu_trap_reg:reset_l , trap:trap_w_reg:reset_l , trap:brtaken_reg:reset_l , ex_regs:lockcount0_cacheon_reg:lc0_co_reset_l , ex_regs:psr_bm8_reg:reset_l , ex_regs:lockcount1_cacheon_reg:lc1_co_reset_l , ic_cntl:iu_psr_ice_reg:reset_l , ff_sre_10:ff_sre_0:reset_l , ff_sre_10:ff_sre_1:reset_l , ff_sre_10:ff_sre_2:reset_l , ff_sre_10:ff_sre_3:reset_l , ff_sre_10:ff_sre_4:reset_l , ff_sre_10:ff_sre_5:reset_l , ff_sre_10:ff_sre_6:reset_l , ff_sre_10:ff_sre_7:reset_l , ff_sre_10:ff_sre_8:reset_l , ff_sre_10:ff_sre_9:reset_l , ff_sre_11:ff_sre_0:reset_l , ff_sre_11:ff_sre_1:reset_l , ff_sre_11:ff_sre_2:reset_l , ff_sre_11:ff_sre_3:reset_l , ff_sre_11:ff_sre_4:reset_l , ff_sre_11:ff_sre_5:reset_l , ff_sre_11:ff_sre_6:reset_l , ff_sre_11:ff_sre_7:reset_l , ff_sre_11:ff_sre_8:reset_l , ff_sre_11:ff_sre_9:reset_l , ff_sre_11:ff_sre_10:reset_l , ff_sre_12:ff_sre_0:reset_l , ff_sre_12:ff_sre_1:reset_l , ff_sre_12:ff_sre_2:reset_l , ff_sre_12:ff_sre_3:reset_l , ff_sre_12:ff_sre_4:reset_l , ff_sre_12:ff_sre_5:reset_l , ff_sre_12:ff_sre_6:reset_l , ff_sre_12:ff_sre_7:reset_l , ff_sre_12:ff_sre_8:reset_l , ff_sre_12:ff_sre_9:reset_l , ff_sre_12:ff_sre_10:reset_l , ff_sre_12:ff_sre_11:reset_l , ff_sre_13:ff_sre_0:reset_l , ff_sre_13:ff_sre_1:reset_l , ff_sre_13:ff_sre_2:reset_l , ff_sre_13:ff_sre_3:reset_l , ff_sre_13:ff_sre_4:reset_l , ff_sre_13:ff_sre_5:reset_l , ff_sre_13:ff_sre_6:reset_l , ff_sre_13:ff_sre_7:reset_l , ff_sre_13:ff_sre_8:reset_l , ff_sre_13:ff_sre_9:reset_l , ff_sre_13:ff_sre_10:reset_l , ff_sre_13:ff_sre_11:reset_l , ff_sre_13:ff_sre_12:reset_l , ff_sre_14:ff_sre_0:reset_l , ff_sre_14:ff_sre_1:reset_l , ff_sre_14:ff_sre_2:reset_l , ff_sre_14:ff_sre_3:reset_l , ff_sre_14:ff_sre_4:reset_l , ff_sre_14:ff_sre_5:reset_l , ff_sre_14:ff_sre_6:reset_l , ff_sre_14:ff_sre_7:reset_l , ff_sre_14:ff_sre_8:reset_l , ff_sre_14:ff_sre_9:reset_l , ff_sre_14:ff_sre_10:reset_l , ff_sre_14:ff_sre_11:reset_l , ff_sre_14:ff_sre_12:reset_l , ff_sre_14:ff_sre_13:reset_l , ff_sre_15:ff_sre_0:reset_l , ff_sre_15:ff_sre_1:reset_l , ff_sre_15:ff_sre_2:reset_l , ff_sre_15:ff_sre_3:reset_l , ff_sre_15:ff_sre_4:reset_l , ff_sre_15:ff_sre_5:reset_l , ff_sre_15:ff_sre_6:reset_l , ff_sre_15:ff_sre_7:reset_l , ff_sre_15:ff_sre_8:reset_l , ff_sre_15:ff_sre_9:reset_l , ff_sre_15:ff_sre_10:reset_l , ff_sre_15:ff_sre_11:reset_l , ff_sre_15:ff_sre_12:reset_l , ff_sre_15:ff_sre_13:reset_l , ff_sre_15:ff_sre_14:reset_l , ff_sre_16:ff_sre_0:reset_l , ff_sre_16:ff_sre_1:reset_l , ff_sre_16:ff_sre_2:reset_l , ff_sre_16:ff_sre_3:reset_l , ff_sre_16:ff_sre_4:reset_l , ff_sre_16:ff_sre_5:reset_l , ff_sre_16:ff_sre_6:reset_l , ff_sre_16:ff_sre_7:reset_l , ff_sre_16:ff_sre_8:reset_l , ff_sre_16:ff_sre_9:reset_l , ff_sre_16:ff_sre_10:reset_l , ff_sre_16:ff_sre_11:reset_l , ff_sre_16:ff_sre_12:reset_l , ff_sre_16:ff_sre_13:reset_l , ff_sre_16:ff_sre_14:reset_l , ff_sre_16:ff_sre_15:reset_l , ff_sre_17:ff_sre_0:reset_l , ff_sre_17:ff_sre_1:reset_l , ff_sre_17:ff_sre_2:reset_l , ff_sre_17:ff_sre_3:reset_l , ff_sre_17:ff_sre_4:reset_l , ff_sre_17:ff_sre_5:reset_l , ff_sre_17:ff_sre_6:reset_l , ff_sre_17:ff_sre_7:reset_l , ff_sre_17:ff_sre_8:reset_l , ff_sre_17:ff_sre_9:reset_l , ff_sre_17:ff_sre_10:reset_l , ff_sre_17:ff_sre_11:reset_l , ff_sre_17:ff_sre_12:reset_l , ff_sre_17:ff_sre_13:reset_l , ff_sre_17:ff_sre_14:reset_l , ff_sre_17:ff_sre_15:reset_l , ff_sre_17:ff_sre_16:reset_l , ff_sre_18:ff_sre_0:reset_l , ff_sre_18:ff_sre_1:reset_l , ff_sre_18:ff_sre_2:reset_l , ff_sre_18:ff_sre_3:reset_l , ff_sre_18:ff_sre_4:reset_l , ff_sre_18:ff_sre_5:reset_l , ff_sre_18:ff_sre_6:reset_l , ff_sre_18:ff_sre_7:reset_l , ff_sre_18:ff_sre_8:reset_l , ff_sre_18:ff_sre_9:reset_l , ff_sre_18:ff_sre_10:reset_l , ff_sre_18:ff_sre_11:reset_l , ff_sre_18:ff_sre_12:reset_l , ff_sre_18:ff_sre_13:reset_l , ff_sre_18:ff_sre_14:reset_l , ff_sre_18:ff_sre_15:reset_l , ff_sre_18:ff_sre_16:reset_l , ff_sre_18:ff_sre_17:reset_l , ff_sre_19:ff_sre_0:reset_l , ff_sre_19:ff_sre_1:reset_l , ff_sre_19:ff_sre_2:reset_l , ff_sre_19:ff_sre_3:reset_l , ff_sre_19:ff_sre_4:reset_l , ff_sre_19:ff_sre_5:reset_l , ff_sre_19:ff_sre_6:reset_l , ff_sre_19:ff_sre_7:reset_l , ff_sre_19:ff_sre_8:reset_l , ff_sre_19:ff_sre_9:reset_l , ff_sre_19:ff_sre_10:reset_l , ff_sre_19:ff_sre_11:reset_l , ff_sre_19:ff_sre_12:reset_l , ff_sre_19:ff_sre_13:reset_l , ff_sre_19:ff_sre_14:reset_l , ff_sre_19:ff_sre_15:reset_l , ff_sre_19:ff_sre_16:reset_l , ff_sre_19:ff_sre_17:reset_l , ff_sre_19:ff_sre_18:reset_l , ff_sre_20:ff_sre_0:reset_l , ff_sre_20:ff_sre_1:reset_l , ff_sre_20:ff_sre_2:reset_l , ff_sre_20:ff_sre_3:reset_l , ff_sre_20:ff_sre_4:reset_l , ff_sre_20:ff_sre_5:reset_l , ff_sre_20:ff_sre_6:reset_l , ff_sre_20:ff_sre_7:reset_l , ff_sre_20:ff_sre_8:reset_l , ff_sre_20:ff_sre_9:reset_l , ff_sre_20:ff_sre_10:reset_l , ff_sre_20:ff_sre_11:reset_l , ff_sre_20:ff_sre_12:reset_l , ff_sre_20:ff_sre_13:reset_l , ff_sre_20:ff_sre_14:reset_l , ff_sre_20:ff_sre_15:reset_l , ff_sre_20:ff_sre_16:reset_l , ff_sre_20:ff_sre_17:reset_l , ff_sre_20:ff_sre_18:reset_l , ff_sre_20:ff_sre_19:reset_l , ff_sre_21:ff_sre_0:reset_l , ff_sre_21:ff_sre_1:reset_l , ff_sre_21:ff_sre_2:reset_l , ff_sre_21:ff_sre_3:reset_l , ff_sre_21:ff_sre_4:reset_l , ff_sre_21:ff_sre_5:reset_l , ff_sre_21:ff_sre_6:reset_l , ff_sre_21:ff_sre_7:reset_l , ff_sre_21:ff_sre_8:reset_l , ff_sre_21:ff_sre_9:reset_l , ff_sre_21:ff_sre_10:reset_l , ff_sre_21:ff_sre_11:reset_l , ff_sre_21:ff_sre_12:reset_l , ff_sre_21:ff_sre_13:reset_l , ff_sre_21:ff_sre_14:reset_l , ff_sre_21:ff_sre_15:reset_l , ff_sre_21:ff_sre_16:reset_l , ff_sre_21:ff_sre_17:reset_l , ff_sre_21:ff_sre_18:reset_l , ff_sre_21:ff_sre_19:reset_l , ff_sre_21:ff_sre_20:reset_l , ff_sre_22:ff_sre_0:reset_l , ff_sre_22:ff_sre_1:reset_l , ff_sre_22:ff_sre_2:reset_l , ff_sre_22:ff_sre_3:reset_l , ff_sre_22:ff_sre_4:reset_l , ff_sre_22:ff_sre_5:reset_l , ff_sre_22:ff_sre_6:reset_l , ff_sre_22:ff_sre_7:reset_l , ff_sre_22:ff_sre_8:reset_l , ff_sre_22:ff_sre_9:reset_l , ff_sre_22:ff_sre_10:reset_l , ff_sre_22:ff_sre_11:reset_l , ff_sre_22:ff_sre_12:reset_l , ff_sre_22:ff_sre_13:reset_l , ff_sre_22:ff_sre_14:reset_l , ff_sre_22:ff_sre_15:reset_l , ff_sre_22:ff_sre_16:reset_l , ff_sre_22:ff_sre_17:reset_l , ff_sre_22:ff_sre_18:reset_l , ff_sre_22:ff_sre_19:reset_l , ff_sre_22:ff_sre_20:reset_l , ff_sre_22:ff_sre_21:reset_l , ff_sre_23:ff_sre_0:reset_l , ff_sre_23:ff_sre_1:reset_l , ff_sre_23:ff_sre_2:reset_l , ff_sre_23:ff_sre_3:reset_l , ff_sre_23:ff_sre_4:reset_l , ff_sre_23:ff_sre_5:reset_l , ff_sre_23:ff_sre_6:reset_l , ff_sre_23:ff_sre_7:reset_l , ff_sre_23:ff_sre_8:reset_l , ff_sre_23:ff_sre_9:reset_l , ff_sre_23:ff_sre_10:reset_l , ff_sre_23:ff_sre_11:reset_l , ff_sre_23:ff_sre_12:reset_l , ff_sre_23:ff_sre_13:reset_l , ff_sre_23:ff_sre_14:reset_l , ff_sre_23:ff_sre_15:reset_l , ff_sre_23:ff_sre_16:reset_l , ff_sre_23:ff_sre_17:reset_l , ff_sre_23:ff_sre_18:reset_l , ff_sre_23:ff_sre_19:reset_l , ff_sre_23:ff_sre_20:reset_l , ff_sre_23:ff_sre_21:reset_l , ff_sre_23:ff_sre_22:reset_l , ff_sre_24:ff_sre_0:reset_l , ff_sre_24:ff_sre_1:reset_l , ff_sre_24:ff_sre_2:reset_l , ff_sre_24:ff_sre_3:reset_l , ff_sre_24:ff_sre_4:reset_l , ff_sre_24:ff_sre_5:reset_l , ff_sre_24:ff_sre_6:reset_l , ff_sre_24:ff_sre_7:reset_l , ff_sre_24:ff_sre_8:reset_l , ff_sre_24:ff_sre_9:reset_l , ff_sre_24:ff_sre_10:reset_l , ff_sre_24:ff_sre_11:reset_l , ff_sre_24:ff_sre_12:reset_l , ff_sre_24:ff_sre_13:reset_l , ff_sre_24:ff_sre_14:reset_l , ff_sre_24:ff_sre_15:reset_l , ff_sre_24:ff_sre_16:reset_l , ff_sre_24:ff_sre_17:reset_l , ff_sre_24:ff_sre_18:reset_l , ff_sre_24:ff_sre_19:reset_l , ff_sre_24:ff_sre_20:reset_l , ff_sre_24:ff_sre_21:reset_l , ff_sre_24:ff_sre_22:reset_l , ff_sre_24:ff_sre_23:reset_l , ff_sre_25:ff_sre_0:reset_l , ff_sre_25:ff_sre_1:reset_l , ff_sre_25:ff_sre_2:reset_l , ff_sre_25:ff_sre_3:reset_l , ff_sre_25:ff_sre_4:reset_l , ff_sre_25:ff_sre_5:reset_l , ff_sre_25:ff_sre_6:reset_l , ff_sre_25:ff_sre_7:reset_l , ff_sre_25:ff_sre_8:reset_l , ff_sre_25:ff_sre_9:reset_l , ff_sre_25:ff_sre_10:reset_l , ff_sre_25:ff_sre_11:reset_l , ff_sre_25:ff_sre_12:reset_l , ff_sre_25:ff_sre_13:reset_l , ff_sre_25:ff_sre_14:reset_l , ff_sre_25:ff_sre_15:reset_l , ff_sre_25:ff_sre_16:reset_l , ff_sre_25:ff_sre_17:reset_l , ff_sre_25:ff_sre_18:reset_l , ff_sre_25:ff_sre_19:reset_l , ff_sre_25:ff_sre_20:reset_l , ff_sre_25:ff_sre_21:reset_l , ff_sre_25:ff_sre_22:reset_l , ff_sre_25:ff_sre_23:reset_l , ff_sre_25:ff_sre_24:reset_l , ff_sre_26:ff_sre_0:reset_l , ff_sre_26:ff_sre_1:reset_l , ff_sre_26:ff_sre_2:reset_l , ff_sre_26:ff_sre_3:reset_l , ff_sre_26:ff_sre_4:reset_l , ff_sre_26:ff_sre_5:reset_l , ff_sre_26:ff_sre_6:reset_l , ff_sre_26:ff_sre_7:reset_l , ff_sre_26:ff_sre_8:reset_l , ff_sre_26:ff_sre_9:reset_l , ff_sre_26:ff_sre_10:reset_l , ff_sre_26:ff_sre_11:reset_l , ff_sre_26:ff_sre_12:reset_l , ff_sre_26:ff_sre_13:reset_l , ff_sre_26:ff_sre_14:reset_l , ff_sre_26:ff_sre_15:reset_l , ff_sre_26:ff_sre_16:reset_l , ff_sre_26:ff_sre_17:reset_l , ff_sre_26:ff_sre_18:reset_l , ff_sre_26:ff_sre_19:reset_l , ff_sre_26:ff_sre_20:reset_l , ff_sre_26:ff_sre_21:reset_l , ff_sre_26:ff_sre_22:reset_l , ff_sre_26:ff_sre_23:reset_l , ff_sre_26:ff_sre_24:reset_l , ff_sre_26:ff_sre_25:reset_l , ff_sre_27:ff_sre_0:reset_l , ff_sre_27:ff_sre_1:reset_l , ff_sre_27:ff_sre_2:reset_l , ff_sre_27:ff_sre_3:reset_l , ff_sre_27:ff_sre_4:reset_l , ff_sre_27:ff_sre_5:reset_l , ff_sre_27:ff_sre_6:reset_l , ff_sre_27:ff_sre_7:reset_l , ff_sre_27:ff_sre_8:reset_l , ff_sre_27:ff_sre_9:reset_l , ff_sre_27:ff_sre_10:reset_l , ff_sre_27:ff_sre_11:reset_l , ff_sre_27:ff_sre_12:reset_l , ff_sre_27:ff_sre_13:reset_l , ff_sre_27:ff_sre_14:reset_l , ff_sre_27:ff_sre_15:reset_l , ff_sre_27:ff_sre_16:reset_l , ff_sre_27:ff_sre_17:reset_l , ff_sre_27:ff_sre_18:reset_l , ff_sre_27:ff_sre_19:reset_l , ff_sre_27:ff_sre_20:reset_l , ff_sre_27:ff_sre_21:reset_l , ff_sre_27:ff_sre_22:reset_l , ff_sre_27:ff_sre_23:reset_l , ff_sre_27:ff_sre_24:reset_l , ff_sre_27:ff_sre_25:reset_l , ff_sre_27:ff_sre_26:reset_l , ff_sre_28:ff_sre_0:reset_l , ff_sre_28:ff_sre_1:reset_l , ff_sre_28:ff_sre_2:reset_l , ff_sre_28:ff_sre_3:reset_l , ff_sre_28:ff_sre_4:reset_l , ff_sre_28:ff_sre_5:reset_l , ff_sre_28:ff_sre_6:reset_l , ff_sre_28:ff_sre_7:reset_l , ff_sre_28:ff_sre_8:reset_l , ff_sre_28:ff_sre_9:reset_l , ff_sre_28:ff_sre_10:reset_l , ff_sre_28:ff_sre_11:reset_l , ff_sre_28:ff_sre_12:reset_l , ff_sre_28:ff_sre_13:reset_l , ff_sre_28:ff_sre_14:reset_l , ff_sre_28:ff_sre_15:reset_l , ff_sre_28:ff_sre_16:reset_l , ff_sre_28:ff_sre_17:reset_l , ff_sre_28:ff_sre_18:reset_l , ff_sre_28:ff_sre_19:reset_l , ff_sre_28:ff_sre_20:reset_l , ff_sre_28:ff_sre_21:reset_l , ff_sre_28:ff_sre_22:reset_l , ff_sre_28:ff_sre_23:reset_l , ff_sre_28:ff_sre_24:reset_l , ff_sre_28:ff_sre_25:reset_l , ff_sre_28:ff_sre_26:reset_l , ff_sre_28:ff_sre_27:reset_l , ff_sre_29:ff_sre_0:reset_l , ff_sre_29:ff_sre_1:reset_l , ff_sre_29:ff_sre_2:reset_l , ff_sre_29:ff_sre_3:reset_l , ff_sre_29:ff_sre_4:reset_l , ff_sre_29:ff_sre_5:reset_l , ff_sre_29:ff_sre_6:reset_l , ff_sre_29:ff_sre_7:reset_l , ff_sre_29:ff_sre_8:reset_l , ff_sre_29:ff_sre_9:reset_l , ff_sre_29:ff_sre_10:reset_l , ff_sre_29:ff_sre_11:reset_l , ff_sre_29:ff_sre_12:reset_l , ff_sre_29:ff_sre_13:reset_l , ff_sre_29:ff_sre_14:reset_l , ff_sre_29:ff_sre_15:reset_l , ff_sre_29:ff_sre_16:reset_l , ff_sre_29:ff_sre_17:reset_l , ff_sre_29:ff_sre_18:reset_l , ff_sre_29:ff_sre_19:reset_l , ff_sre_29:ff_sre_20:reset_l , ff_sre_29:ff_sre_21:reset_l , ff_sre_29:ff_sre_22:reset_l , ff_sre_29:ff_sre_23:reset_l , ff_sre_29:ff_sre_24:reset_l , ff_sre_29:ff_sre_25:reset_l , ff_sre_29:ff_sre_26:reset_l , ff_sre_29:ff_sre_27:reset_l , ff_sre_29:ff_sre_28:reset_l , ff_sre_30:ff_sre_0:reset_l , ff_sre_30:ff_sre_1:reset_l , ff_sre_30:ff_sre_2:reset_l , ff_sre_30:ff_sre_3:reset_l , ff_sre_30:ff_sre_4:reset_l , ff_sre_30:ff_sre_5:reset_l , ff_sre_30:ff_sre_6:reset_l , ff_sre_30:ff_sre_7:reset_l , ff_sre_30:ff_sre_8:reset_l , ff_sre_30:ff_sre_9:reset_l , ff_sre_30:ff_sre_10:reset_l , ff_sre_30:ff_sre_11:reset_l , ff_sre_30:ff_sre_12:reset_l , ff_sre_30:ff_sre_13:reset_l , ff_sre_30:ff_sre_14:reset_l , ff_sre_30:ff_sre_15:reset_l , ff_sre_30:ff_sre_16:reset_l , ff_sre_30:ff_sre_17:reset_l , ff_sre_30:ff_sre_18:reset_l , ff_sre_30:ff_sre_19:reset_l , ff_sre_30:ff_sre_20:reset_l , ff_sre_30:ff_sre_21:reset_l , ff_sre_30:ff_sre_22:reset_l , ff_sre_30:ff_sre_23:reset_l , ff_sre_30:ff_sre_24:reset_l , ff_sre_30:ff_sre_25:reset_l , ff_sre_30:ff_sre_26:reset_l , ff_sre_30:ff_sre_27:reset_l , ff_sre_30:ff_sre_28:reset_l , ff_sre_30:ff_sre_29:reset_l , ff_sre_31:ff_sre_0:reset_l , ff_sre_31:ff_sre_1:reset_l , ff_sre_31:ff_sre_2:reset_l , ff_sre_31:ff_sre_3:reset_l , ff_sre_31:ff_sre_4:reset_l , ff_sre_31:ff_sre_5:reset_l , ff_sre_31:ff_sre_6:reset_l , ff_sre_31:ff_sre_7:reset_l , ff_sre_31:ff_sre_8:reset_l , ff_sre_31:ff_sre_9:reset_l , ff_sre_31:ff_sre_10:reset_l , ff_sre_31:ff_sre_11:reset_l , ff_sre_31:ff_sre_12:reset_l , ff_sre_31:ff_sre_13:reset_l , ff_sre_31:ff_sre_14:reset_l , ff_sre_31:ff_sre_15:reset_l , ff_sre_31:ff_sre_16:reset_l , ff_sre_31:ff_sre_17:reset_l , ff_sre_31:ff_sre_18:reset_l , ff_sre_31:ff_sre_19:reset_l , ff_sre_31:ff_sre_20:reset_l , ff_sre_31:ff_sre_21:reset_l , ff_sre_31:ff_sre_22:reset_l , ff_sre_31:ff_sre_23:reset_l , ff_sre_31:ff_sre_24:reset_l , ff_sre_31:ff_sre_25:reset_l , ff_sre_31:ff_sre_26:reset_l , ff_sre_31:ff_sre_27:reset_l , ff_sre_31:ff_sre_28:reset_l , ff_sre_31:ff_sre_29:reset_l , ff_sre_31:ff_sre_30:reset_l , ff_sre_32:ff_sre_0:reset_l , ff_sre_32:ff_sre_1:reset_l , ff_sre_32:ff_sre_2:reset_l , ff_sre_32:ff_sre_3:reset_l , ff_sre_32:ff_sre_4:reset_l , ff_sre_32:ff_sre_5:reset_l , ff_sre_32:ff_sre_6:reset_l , ff_sre_32:ff_sre_7:reset_l , ff_sre_32:ff_sre_8:reset_l , ff_sre_32:ff_sre_9:reset_l , ff_sre_32:ff_sre_10:reset_l , ff_sre_32:ff_sre_11:reset_l , ff_sre_32:ff_sre_12:reset_l , ff_sre_32:ff_sre_13:reset_l , ff_sre_32:ff_sre_14:reset_l , ff_sre_32:ff_sre_15:reset_l , ff_sre_32:ff_sre_16:reset_l , ff_sre_32:ff_sre_17:reset_l , ff_sre_32:ff_sre_18:reset_l , ff_sre_32:ff_sre_19:reset_l , ff_sre_32:ff_sre_20:reset_l , ff_sre_32:ff_sre_21:reset_l , ff_sre_32:ff_sre_22:reset_l , ff_sre_32:ff_sre_23:reset_l , ff_sre_32:ff_sre_24:reset_l , ff_sre_32:ff_sre_25:reset_l , ff_sre_32:ff_sre_26:reset_l , ff_sre_32:ff_sre_27:reset_l , ff_sre_32:ff_sre_28:reset_l , ff_sre_32:ff_sre_29:reset_l , ff_sre_32:ff_sre_30:reset_l , ff_sre_32:ff_sre_31:reset_l , smu_ctl:load_c_flop:reset_l , smu_ctl:store_c_flop:reset_l , ff_sre_40:ff_sre_0:reset_l , ff_sre_40:ff_sre_1:reset_l , ff_sre_40:ff_sre_2:reset_l , ff_sre_40:ff_sre_3:reset_l , ff_sre_40:ff_sre_4:reset_l , ff_sre_40:ff_sre_5:reset_l , ff_sre_40:ff_sre_6:reset_l , ff_sre_40:ff_sre_7:reset_l , ff_sre_40:ff_sre_8:reset_l , ff_sre_40:ff_sre_9:reset_l , ff_sre_40:ff_sre_10:reset_l , ff_sre_40:ff_sre_11:reset_l , ff_sre_40:ff_sre_12:reset_l , ff_sre_40:ff_sre_13:reset_l , ff_sre_40:ff_sre_14:reset_l , ff_sre_40:ff_sre_15:reset_l , ff_sre_40:ff_sre_16:reset_l , ff_sre_40:ff_sre_17:reset_l , ff_sre_40:ff_sre_18:reset_l , ff_sre_40:ff_sre_19:reset_l , ff_sre_40:ff_sre_20:reset_l , ff_sre_40:ff_sre_21:reset_l , ff_sre_40:ff_sre_22:reset_l , ff_sre_40:ff_sre_23:reset_l , ff_sre_40:ff_sre_24:reset_l , ff_sre_40:ff_sre_25:reset_l , ff_sre_40:ff_sre_26:reset_l , ff_sre_40:ff_sre_27:reset_l , ff_sre_40:ff_sre_28:reset_l , ff_sre_40:ff_sre_29:reset_l , ff_sre_40:ff_sre_30:reset_l , ff_sre_40:ff_sre_31:reset_l , ff_sre_40:ff_sre_32:reset_l , ff_sre_40:ff_sre_33:reset_l , ff_sre_40:ff_sre_34:reset_l , ff_sre_40:ff_sre_35:reset_l , ff_sre_40:ff_sre_36:reset_l , ff_sre_40:ff_sre_37:reset_l , ff_sre_40:ff_sre_38:reset_l , ff_sre_40:ff_sre_39:reset_l , biu_ctl:arb_select_state:reset_l , hold_logic:first_cyc_e_reg:reset_l , hold_logic:fphold_reg:reset_l , dc_dec:nc_c2_reg:reset_l , rcu_ctl:flop_data_we_e:reset_l , rcu_ctl:flop_data_we_c:reset_l , rcu_ctl:flop_global_we_e:reset_l , rcu_ctl:flop_global_we_c:reset_l , rcu_ctl:flop_fc_e:reset_l , rcu_ctl:flop_fc_c:reset_l , rcu_ctl:flop_udone_c:reset_l , rcu_ctl:flop_udone_w:reset_l 
 reset_l : ff_sre_10 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l 
 reset_l : ff_sre_11 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l 
 reset_l : ff_sre_12 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l 
 reset_l : ff_sre_13 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l 
 reset_l : ff_sre_14 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l 
 reset_l : ff_sre_15 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l 
 reset_l : ff_sre_16 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l 
Connects up to:ucode_ind:ff_sre_16_1:reset_l 
 reset_l : ff_sre_17 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l , ff_sre:ff_sre_16:reset_l 
 reset_l : ff_sre_18 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l , ff_sre:ff_sre_16:reset_l , ff_sre:ff_sre_17:reset_l 
 reset_l : ff_sre_19 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l , ff_sre:ff_sre_16:reset_l , ff_sre:ff_sre_17:reset_l , ff_sre:ff_sre_18:reset_l 
Connects up to:ex_ctl:reg_wr_mux_sel_raw_e_reg:reset_l 
 reset_l : ff_sre_2 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l 
Connects up to:ex_ctl:bit_cvt_mux_sel_reg:reset_l , ex_ctl:iu_data_mux_sel_reg:reset_l , ex_ctl:ucode_rd_part_dcache_c_reg:reset_l , ex_ctl:adder_src1_mux_sel_raw_ereg:reset_l 
 reset_l : ff_sre_20 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l , ff_sre:ff_sre_16:reset_l , ff_sre:ff_sre_17:reset_l , ff_sre:ff_sre_18:reset_l , ff_sre:ff_sre_19:reset_l 
 reset_l : ff_sre_21 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l , ff_sre:ff_sre_16:reset_l , ff_sre:ff_sre_17:reset_l , ff_sre:ff_sre_18:reset_l , ff_sre:ff_sre_19:reset_l , ff_sre:ff_sre_20:reset_l 
Connects up to:ex_ctl:reg_rd_mux_sel_raw_e_reg:reset_l 
 reset_l : ff_sre_22 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l , ff_sre:ff_sre_16:reset_l , ff_sre:ff_sre_17:reset_l , ff_sre:ff_sre_18:reset_l , ff_sre:ff_sre_19:reset_l , ff_sre:ff_sre_20:reset_l , ff_sre:ff_sre_21:reset_l 
 reset_l : ff_sre_23 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l , ff_sre:ff_sre_16:reset_l , ff_sre:ff_sre_17:reset_l , ff_sre:ff_sre_18:reset_l , ff_sre:ff_sre_19:reset_l , ff_sre:ff_sre_20:reset_l , ff_sre:ff_sre_21:reset_l , ff_sre:ff_sre_22:reset_l 
 reset_l : ff_sre_24 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l , ff_sre:ff_sre_16:reset_l , ff_sre:ff_sre_17:reset_l , ff_sre:ff_sre_18:reset_l , ff_sre:ff_sre_19:reset_l , ff_sre:ff_sre_20:reset_l , ff_sre:ff_sre_21:reset_l , ff_sre:ff_sre_22:reset_l , ff_sre:ff_sre_23:reset_l 
 reset_l : ff_sre_25 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l , ff_sre:ff_sre_16:reset_l , ff_sre:ff_sre_17:reset_l , ff_sre:ff_sre_18:reset_l , ff_sre:ff_sre_19:reset_l , ff_sre:ff_sre_20:reset_l , ff_sre:ff_sre_21:reset_l , ff_sre:ff_sre_22:reset_l , ff_sre:ff_sre_23:reset_l , ff_sre:ff_sre_24:reset_l 
 reset_l : ff_sre_26 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l , ff_sre:ff_sre_16:reset_l , ff_sre:ff_sre_17:reset_l , ff_sre:ff_sre_18:reset_l , ff_sre:ff_sre_19:reset_l , ff_sre:ff_sre_20:reset_l , ff_sre:ff_sre_21:reset_l , ff_sre:ff_sre_22:reset_l , ff_sre:ff_sre_23:reset_l , ff_sre:ff_sre_24:reset_l , ff_sre:ff_sre_25:reset_l 
 reset_l : ff_sre_27 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l , ff_sre:ff_sre_16:reset_l , ff_sre:ff_sre_17:reset_l , ff_sre:ff_sre_18:reset_l , ff_sre:ff_sre_19:reset_l , ff_sre:ff_sre_20:reset_l , ff_sre:ff_sre_21:reset_l , ff_sre:ff_sre_22:reset_l , ff_sre:ff_sre_23:reset_l , ff_sre:ff_sre_24:reset_l , ff_sre:ff_sre_25:reset_l , ff_sre:ff_sre_26:reset_l 
 reset_l : ff_sre_28 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l , ff_sre:ff_sre_16:reset_l , ff_sre:ff_sre_17:reset_l , ff_sre:ff_sre_18:reset_l , ff_sre:ff_sre_19:reset_l , ff_sre:ff_sre_20:reset_l , ff_sre:ff_sre_21:reset_l , ff_sre:ff_sre_22:reset_l , ff_sre:ff_sre_23:reset_l , ff_sre:ff_sre_24:reset_l , ff_sre:ff_sre_25:reset_l , ff_sre:ff_sre_26:reset_l , ff_sre:ff_sre_27:reset_l 
 reset_l : ff_sre_29 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l , ff_sre:ff_sre_16:reset_l , ff_sre:ff_sre_17:reset_l , ff_sre:ff_sre_18:reset_l , ff_sre:ff_sre_19:reset_l , ff_sre:ff_sre_20:reset_l , ff_sre:ff_sre_21:reset_l , ff_sre:ff_sre_22:reset_l , ff_sre:ff_sre_23:reset_l , ff_sre:ff_sre_24:reset_l , ff_sre:ff_sre_25:reset_l , ff_sre:ff_sre_26:reset_l , ff_sre:ff_sre_27:reset_l , ff_sre:ff_sre_28:reset_l 
 reset_l : ff_sre_3 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l 
Connects up to:ifu:flop_offset_br:reset_l , ifu:flop_inst_fold_r:reset_l , ifu:flop_inst_fold_e:reset_l , ifu:flop_inst_fold_c:reset_l , ex_ctl:baload_e_reg:reset_l , ex_ctl:bastore_e_reg:reset_l , ex_ctl:iu_dcu_flush_e_flop:reset_l , ex_ctl:load_data_mux_sel_e_reg:reset_l , ex_ctl:load_data_mux_sel_reg:reset_l , ex_ctl:cmp_mux_sel_reg:reset_l , ex_ctl:shifter_src2_mux_sel_reg:reset_l 
 reset_l : ff_sre_30 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l , ff_sre:ff_sre_16:reset_l , ff_sre:ff_sre_17:reset_l , ff_sre:ff_sre_18:reset_l , ff_sre:ff_sre_19:reset_l , ff_sre:ff_sre_20:reset_l , ff_sre:ff_sre_21:reset_l , ff_sre:ff_sre_22:reset_l , ff_sre:ff_sre_23:reset_l , ff_sre:ff_sre_24:reset_l , ff_sre:ff_sre_25:reset_l , ff_sre:ff_sre_26:reset_l , ff_sre:ff_sre_27:reset_l , ff_sre:ff_sre_28:reset_l , ff_sre:ff_sre_29:reset_l 
Connects up to:ex_regs:lockaddr0_reg:lock0_uncache , ex_regs:lockaddr1_reg:lock1_uncache 
 reset_l : ff_sre_31 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l , ff_sre:ff_sre_16:reset_l , ff_sre:ff_sre_17:reset_l , ff_sre:ff_sre_18:reset_l , ff_sre:ff_sre_19:reset_l , ff_sre:ff_sre_20:reset_l , ff_sre:ff_sre_21:reset_l , ff_sre:ff_sre_22:reset_l , ff_sre:ff_sre_23:reset_l , ff_sre:ff_sre_24:reset_l , ff_sre:ff_sre_25:reset_l , ff_sre:ff_sre_26:reset_l , ff_sre:ff_sre_27:reset_l , ff_sre:ff_sre_28:reset_l , ff_sre:ff_sre_29:reset_l , ff_sre:ff_sre_30:reset_l 
 reset_l : ff_sre_32 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l , ff_sre:ff_sre_16:reset_l , ff_sre:ff_sre_17:reset_l , ff_sre:ff_sre_18:reset_l , ff_sre:ff_sre_19:reset_l , ff_sre:ff_sre_20:reset_l , ff_sre:ff_sre_21:reset_l , ff_sre:ff_sre_22:reset_l , ff_sre:ff_sre_23:reset_l , ff_sre:ff_sre_24:reset_l , ff_sre:ff_sre_25:reset_l , ff_sre:ff_sre_26:reset_l , ff_sre:ff_sre_27:reset_l , ff_sre:ff_sre_28:reset_l , ff_sre:ff_sre_29:reset_l , ff_sre:ff_sre_30:reset_l , ff_sre:ff_sre_31:reset_l 
Connects up to:ucode_dat:reg_areg0:reg_clear_l , ucode_dat:reg_reg0:reg_clear_l , ucode_dat:reg_reg1:reg_clear_l , ucode_dat:reg_reg2:reg_clear_l , ucode_dat:reg_reg3:reg_clear_l , ucode_dat:reg_reg5:reg_clear_l , ucode_dat:reg_reg6:reg_clear_l , icu_dpath:icu_addr_d1_reg:reset_l , icu_dpath:biu_addr_reg:reset_l , pipe_dpath:arch_pcreg:reset_l 
 reset_l : ff_sre_4 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l 
Connects up to:ex_ctl:iu_d_diag_e_reg:reset_l , ex_ctl:iu_i_diag_e_reg:reset_l , dcudp_cntl:cf_word_addr_reg:reset_l , trap:pj_irl_r_reg:reset_l , trap:pj_irl_e_reg:reset_l , trap:pj_irl_c_reg:reset_l , trap:lock_trap_reg:reset_l , biu_ctl:arb_state_reg:reset_l , dc_dec:smu_miss_stall_reg:reset_l , dc_dec:smu_miss_reg:reset_l , ex_dpath:flop_rs1_bypass_sel:reset_l , ex_dpath:flop_rs2_bypass_sel:reset_l 
 reset_l : ff_sre_40 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l , ff_sre:ff_sre_9:reset_l , ff_sre:ff_sre_10:reset_l , ff_sre:ff_sre_11:reset_l , ff_sre:ff_sre_12:reset_l , ff_sre:ff_sre_13:reset_l , ff_sre:ff_sre_14:reset_l , ff_sre:ff_sre_15:reset_l , ff_sre:ff_sre_16:reset_l , ff_sre:ff_sre_17:reset_l , ff_sre:ff_sre_18:reset_l , ff_sre:ff_sre_19:reset_l , ff_sre:ff_sre_20:reset_l , ff_sre:ff_sre_21:reset_l , ff_sre:ff_sre_22:reset_l , ff_sre:ff_sre_23:reset_l , ff_sre:ff_sre_24:reset_l , ff_sre:ff_sre_25:reset_l , ff_sre:ff_sre_26:reset_l , ff_sre:ff_sre_27:reset_l , ff_sre:ff_sre_28:reset_l , ff_sre:ff_sre_29:reset_l , ff_sre:ff_sre_30:reset_l , ff_sre:ff_sre_31:reset_l , ff_sre:ff_sre_32:reset_l , ff_sre:ff_sre_33:reset_l , ff_sre:ff_sre_34:reset_l , ff_sre:ff_sre_35:reset_l , ff_sre:ff_sre_36:reset_l , ff_sre:ff_sre_37:reset_l , ff_sre:ff_sre_38:reset_l , ff_sre:ff_sre_39:reset_l 
 reset_l : ff_sre_5 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l 
Connects up to:ex_ctl:bit_mux_sel_reg:reset_l , ex_ctl:cvt_mux_sel_reg:reset_l , ex_ctl:shifter_src1_mux_sel_reg:reset_l , ex_ctl:offset_mux_sel_reg:reset_l 
 reset_l : ff_sre_6 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l 
Connects up to:ex_ctl:shift_count_e1_flop:reset_l 
 reset_l : ff_sre_7 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l 
 reset_l : ff_sre_8 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l 
Connects up to:ifu:flop_opcode_1_op:iu_trap_c , ifu:flop_type_rs1:reset_l , ex_ctl:iu_inst_e_reg:reset_l , ex_ctl:opcode_1_op_e_reg:reset_l , ex_ctl:opcode_1_op_c_reg:reset_l , ex_ctl:alu_out_mux_sel_raw_e_reg:reset_l , ex_regs:trapbase_tt_reg:reset_l , dc_dec:iu_miss_stall_reg:reset_l , dc_dec:iu_miss_reg:reset_l 
 reset_l : ff_sre_9 : input
Connects down to:ff_sre:ff_sre_0:reset_l , ff_sre:ff_sre_1:reset_l , ff_sre:ff_sre_2:reset_l , ff_sre:ff_sre_3:reset_l , ff_sre:ff_sre_4:reset_l , ff_sre:ff_sre_5:reset_l , ff_sre:ff_sre_6:reset_l , ff_sre:ff_sre_7:reset_l , ff_sre:ff_sre_8:reset_l 
Connects up to:ucode_seq:seq_addr1_reg:reg_clear_l , ucode_seq:seq_addr2_reg:reg_clear_l , ucode_seq:seq_addr3_reg:reg_clear_l 
 reset_l : ff_sr_10 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l 
 reset_l : ff_sr_11 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l 
 reset_l : ff_sr_12 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l 
 reset_l : ff_sr_13 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l 
 reset_l : ff_sr_14 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l 
 reset_l : ff_sr_15 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l 
 reset_l : ff_sr_16 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l , ff_sr:ff_sr_15:reset_l 
Connects up to:ex_regs:smu_addr_reg:reset_l 
 reset_l : ff_sr_17 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l , ff_sr:ff_sr_15:reset_l , ff_sr:ff_sr_16:reset_l 
 reset_l : ff_sr_18 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l , ff_sr:ff_sr_15:reset_l , ff_sr:ff_sr_16:reset_l , ff_sr:ff_sr_17:reset_l 
 reset_l : ff_sr_19 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l , ff_sr:ff_sr_15:reset_l , ff_sr:ff_sr_16:reset_l , ff_sr:ff_sr_17:reset_l , ff_sr:ff_sr_18:reset_l 
 reset_l : ff_sr_2 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l 
Connects up to:dcudp_cntl:flush_inst_c2_reg:reset_l , pcsu:pcsu_reg_2_1:reset_l , hold_logic:iu_perf_reg:reset_l 
 reset_l : ff_sr_20 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l , ff_sr:ff_sr_15:reset_l , ff_sr:ff_sr_16:reset_l , ff_sr:ff_sr_17:reset_l , ff_sr:ff_sr_18:reset_l , ff_sr:ff_sr_19:reset_l 
 reset_l : ff_sr_21 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l , ff_sr:ff_sr_15:reset_l , ff_sr:ff_sr_16:reset_l , ff_sr:ff_sr_17:reset_l , ff_sr:ff_sr_18:reset_l , ff_sr:ff_sr_19:reset_l , ff_sr:ff_sr_20:reset_l 
 reset_l : ff_sr_22 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l , ff_sr:ff_sr_15:reset_l , ff_sr:ff_sr_16:reset_l , ff_sr:ff_sr_17:reset_l , ff_sr:ff_sr_18:reset_l , ff_sr:ff_sr_19:reset_l , ff_sr:ff_sr_20:reset_l , ff_sr:ff_sr_21:reset_l 
 reset_l : ff_sr_23 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l , ff_sr:ff_sr_15:reset_l , ff_sr:ff_sr_16:reset_l , ff_sr:ff_sr_17:reset_l , ff_sr:ff_sr_18:reset_l , ff_sr:ff_sr_19:reset_l , ff_sr:ff_sr_20:reset_l , ff_sr:ff_sr_21:reset_l , ff_sr:ff_sr_22:reset_l 
 reset_l : ff_sr_24 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l , ff_sr:ff_sr_15:reset_l , ff_sr:ff_sr_16:reset_l , ff_sr:ff_sr_17:reset_l , ff_sr:ff_sr_18:reset_l , ff_sr:ff_sr_19:reset_l , ff_sr:ff_sr_20:reset_l , ff_sr:ff_sr_21:reset_l , ff_sr:ff_sr_22:reset_l , ff_sr:ff_sr_23:reset_l 
 reset_l : ff_sr_25 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l , ff_sr:ff_sr_15:reset_l , ff_sr:ff_sr_16:reset_l , ff_sr:ff_sr_17:reset_l , ff_sr:ff_sr_18:reset_l , ff_sr:ff_sr_19:reset_l , ff_sr:ff_sr_20:reset_l , ff_sr:ff_sr_21:reset_l , ff_sr:ff_sr_22:reset_l , ff_sr:ff_sr_23:reset_l , ff_sr:ff_sr_24:reset_l 
 reset_l : ff_sr_26 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l , ff_sr:ff_sr_15:reset_l , ff_sr:ff_sr_16:reset_l , ff_sr:ff_sr_17:reset_l , ff_sr:ff_sr_18:reset_l , ff_sr:ff_sr_19:reset_l , ff_sr:ff_sr_20:reset_l , ff_sr:ff_sr_21:reset_l , ff_sr:ff_sr_22:reset_l , ff_sr:ff_sr_23:reset_l , ff_sr:ff_sr_24:reset_l , ff_sr:ff_sr_25:reset_l 
 reset_l : ff_sr_27 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l , ff_sr:ff_sr_15:reset_l , ff_sr:ff_sr_16:reset_l , ff_sr:ff_sr_17:reset_l , ff_sr:ff_sr_18:reset_l , ff_sr:ff_sr_19:reset_l , ff_sr:ff_sr_20:reset_l , ff_sr:ff_sr_21:reset_l , ff_sr:ff_sr_22:reset_l , ff_sr:ff_sr_23:reset_l , ff_sr:ff_sr_24:reset_l , ff_sr:ff_sr_25:reset_l , ff_sr:ff_sr_26:reset_l 
 reset_l : ff_sr_28 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l , ff_sr:ff_sr_15:reset_l , ff_sr:ff_sr_16:reset_l , ff_sr:ff_sr_17:reset_l , ff_sr:ff_sr_18:reset_l , ff_sr:ff_sr_19:reset_l , ff_sr:ff_sr_20:reset_l , ff_sr:ff_sr_21:reset_l , ff_sr:ff_sr_22:reset_l , ff_sr:ff_sr_23:reset_l , ff_sr:ff_sr_24:reset_l , ff_sr:ff_sr_25:reset_l , ff_sr:ff_sr_26:reset_l , ff_sr:ff_sr_27:reset_l 
 reset_l : ff_sr_29 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l , ff_sr:ff_sr_15:reset_l , ff_sr:ff_sr_16:reset_l , ff_sr:ff_sr_17:reset_l , ff_sr:ff_sr_18:reset_l , ff_sr:ff_sr_19:reset_l , ff_sr:ff_sr_20:reset_l , ff_sr:ff_sr_21:reset_l , ff_sr:ff_sr_22:reset_l , ff_sr:ff_sr_23:reset_l , ff_sr:ff_sr_24:reset_l , ff_sr:ff_sr_25:reset_l , ff_sr:ff_sr_26:reset_l , ff_sr:ff_sr_27:reset_l , ff_sr:ff_sr_28:reset_l 
 reset_l : ff_sr_3 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l 
Connects up to:ifu:flop_inst_fold_w:reset_l , pipe_cntl:smiss_state_reg:reset_l , pipe_cntl:lduse_state_reg:reset_l , imdr_ctrl:ff_sr_3_1:reset_l , imdr_ctrl:ff_sr_3_2:reset_l , smu_ctl:cs_spill_reg:reset_l , dc_dec:error_reg:reset_l , dc_dec:dcu_perf_reg:reset_l 
 reset_l : ff_sr_30 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l , ff_sr:ff_sr_15:reset_l , ff_sr:ff_sr_16:reset_l , ff_sr:ff_sr_17:reset_l , ff_sr:ff_sr_18:reset_l , ff_sr:ff_sr_19:reset_l , ff_sr:ff_sr_20:reset_l , ff_sr:ff_sr_21:reset_l , ff_sr:ff_sr_22:reset_l , ff_sr:ff_sr_23:reset_l , ff_sr:ff_sr_24:reset_l , ff_sr:ff_sr_25:reset_l , ff_sr:ff_sr_26:reset_l , ff_sr:ff_sr_27:reset_l , ff_sr:ff_sr_28:reset_l , ff_sr:ff_sr_29:reset_l 
 reset_l : ff_sr_31 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l , ff_sr:ff_sr_15:reset_l , ff_sr:ff_sr_16:reset_l , ff_sr:ff_sr_17:reset_l , ff_sr:ff_sr_18:reset_l , ff_sr:ff_sr_19:reset_l , ff_sr:ff_sr_20:reset_l , ff_sr:ff_sr_21:reset_l , ff_sr:ff_sr_22:reset_l , ff_sr:ff_sr_23:reset_l , ff_sr:ff_sr_24:reset_l , ff_sr:ff_sr_25:reset_l , ff_sr:ff_sr_26:reset_l , ff_sr:ff_sr_27:reset_l , ff_sr:ff_sr_28:reset_l , ff_sr:ff_sr_29:reset_l , ff_sr:ff_sr_30:reset_l 
 reset_l : ff_sr_32 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l , ff_sr:ff_sr_9:reset_l , ff_sr:ff_sr_10:reset_l , ff_sr:ff_sr_11:reset_l , ff_sr:ff_sr_12:reset_l , ff_sr:ff_sr_13:reset_l , ff_sr:ff_sr_14:reset_l , ff_sr:ff_sr_15:reset_l , ff_sr:ff_sr_16:reset_l , ff_sr:ff_sr_17:reset_l , ff_sr:ff_sr_18:reset_l , ff_sr:ff_sr_19:reset_l , ff_sr:ff_sr_20:reset_l , ff_sr:ff_sr_21:reset_l , ff_sr:ff_sr_22:reset_l , ff_sr:ff_sr_23:reset_l , ff_sr:ff_sr_24:reset_l , ff_sr:ff_sr_25:reset_l , ff_sr:ff_sr_26:reset_l , ff_sr:ff_sr_27:reset_l , ff_sr:ff_sr_28:reset_l , ff_sr:ff_sr_29:reset_l , ff_sr:ff_sr_30:reset_l , ff_sr:ff_sr_31:reset_l 
 reset_l : ff_sr_4 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l 
Connects up to:pipe_cntl:fold_state_reg:reset_l , imdr_ctrl:ff_sr_4_0:reset_l , imdr_ctrl:ff_sr_4_1:reset_l , smu_ctl:dribb_state_reg:reset_l 
 reset_l : ff_sr_5 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l 
Connects up to:miss_cntl:miss_state_reg:reset_l , miss_cntl:zero_state_reg:reset_l , imdr_ctrl:ff_sr_5_0:reset_l 
 reset_l : ff_sr_6 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l 
Connects up to:imdr_ctrl:ff_sr_6_0:reset_l 
 reset_l : ff_sr_7 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l 
Connects up to:wrbuf_cntl:wb_state_reg:reset_l 
 reset_l : ff_sr_8 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l 
 reset_l : ff_sr_9 : input
Connects down to:ff_sr:ff_sr_0:reset_l , ff_sr:ff_sr_1:reset_l , ff_sr:ff_sr_2:reset_l , ff_sr:ff_sr_3:reset_l , ff_sr:ff_sr_4:reset_l , ff_sr:ff_sr_5:reset_l , ff_sr:ff_sr_6:reset_l , ff_sr:ff_sr_7:reset_l , ff_sr:ff_sr_8:reset_l 
 reset_l : fpu : input
Connects down to:exponent:exp:reset_l , incmod:inc:reset_l , rsadd:rsa:reset_l , prils:prif:reset_l , code_seq:cs:reset_l , nxsign:nxs:reset_l , mantissa:man:reset_l , multmod:mult1:reset_l , mj_spare:i1_spare:reset_l , mj_spare:i2_spare:reset_l , mj_spare:i3_spare:reset_l , mj_spare:i4_spare:reset_l , mj_spare:i5_spare:reset_l , mj_spare:i6_spare:reset_l , mj_spare:i7_spare:reset_l , mj_spare:i8_spare:reset_l , mj_spare:i9_spare:reset_l , mj_spare:i10_spare:reset_l 
 reset_l : fpu_dec : input
Connects down to:mj_s_ff_snre_d_8:ff_fpstate:reset_l 
Connects up to:code_seq_cntl:fpud:reset_l 
 reset_l : fpu_dummy : input
 reset_l : hold_logic : input
Connects down to:ff_sre:first_cyc_e_reg:reset_l , ff_sre:fphold_reg:reset_l , ff_sr_2:iu_perf_reg:reset_l 
Connects up to:iu:hold_logic:reset_l 
 reset_l : ibuffer : input
Connects down to:mj_s_ff_snr_d_32:jmp_pc_d1_reg:reset_l , mj_s_ff_snr_d_32:pc_flop:reset_l 
Connects up to:icu_dpath:ibuffer:reset_l 
 reset_l : ibuf_ctl : input
Connects down to:ibuf_ctl_slice:ibuf_ctl_0:reset_l , ibuf_ctl_slice:ibuf_ctl_1:reset_l , ibuf_ctl_slice:ibuf_ctl_2:reset_l , ibuf_ctl_slice:ibuf_ctl_3:reset_l , ibuf_ctl_slice:ibuf_ctl_4:reset_l , ibuf_ctl_slice:ibuf_ctl_5:reset_l , ibuf_ctl_slice:ibuf_ctl_6:reset_l , ibuf_ctl_slice:ibuf_ctl_7:reset_l , ibuf_ctl_slice:ibuf_ctl_8:reset_l , ibuf_ctl_slice:ibuf_ctl_9:reset_l , ibuf_ctl_slice:ibuf_ctl_10:reset_l , ibuf_ctl_slice:ibuf_ctl_11:reset_l , ibuf_ctl_slice:ibuf_ctl_12:reset_l , ibuf_ctl_slice:ibuf_ctl_13:reset_l , ibuf_ctl_slice:ibuf_ctl_14:reset_l , ibuf_ctl_slice:ibuf_ctl_15:reset_l , ff_sr:squash_vld_reg:reset_l , mj_s_ff_snr_d_8:iu_shift_e_reg:reset_l 
Connects up to:icctl:ibuf_ctl:reset_l 
 reset_l : ibuf_ctl_slice : input
Connects down to:mj_s_ff_snre_d:valid_flop:reset_l , mj_s_ff_snre_d:dirty_flop:reset_l 
Connects up to:ibuf_ctl:ibuf_ctl_0:reset_l , ibuf_ctl:ibuf_ctl_1:reset_l , ibuf_ctl:ibuf_ctl_2:reset_l , ibuf_ctl:ibuf_ctl_3:reset_l , ibuf_ctl:ibuf_ctl_4:reset_l , ibuf_ctl:ibuf_ctl_5:reset_l , ibuf_ctl:ibuf_ctl_6:reset_l , ibuf_ctl:ibuf_ctl_7:reset_l , ibuf_ctl:ibuf_ctl_8:reset_l , ibuf_ctl:ibuf_ctl_9:reset_l , ibuf_ctl:ibuf_ctl_10:reset_l , ibuf_ctl:ibuf_ctl_11:reset_l , ibuf_ctl:ibuf_ctl_12:reset_l , ibuf_ctl:ibuf_ctl_13:reset_l , ibuf_ctl:ibuf_ctl_14:reset_l , ibuf_ctl:ibuf_ctl_15:reset_l 
 reset_l : icctl : input
Connects down to:ic_cntl:ic_cntl:reset_l , ibuf_ctl:ibuf_ctl:reset_l , mj_spare:i1_spare:reset_l , mj_spare:i2_spare:reset_l , mj_spare:i3_spare:reset_l , mj_spare:i4_spare:reset_l , mj_spare:i5_spare:reset_l , mj_spare:i6_spare:reset_l 
Connects up to:icu_nocache:icctl:reset_l , icu:icctl:reset_l 
 reset_l : icu : input
Connects down to:icctl:icctl:reset_l , icu_dpath:icu_dpath:reset_l 
 reset_l : icu_dpath : input
Connects down to:ff_sre_32:icu_addr_d1_reg:reset_l , ff_sre_32:biu_addr_reg:reset_l , mj_s_ff_snr_d:misc_wrd_se_reg:reset_l , ibuffer:ibuffer:reset_l 
Connects up to:icu_nocache:icu_dpath:reset_l , icu:icu_dpath:reset_l 
 reset_l : icu_nocache : input
Connects down to:icctl:icctl:reset_l , icu_dpath:icu_dpath:reset_l 
 reset_l : ic_cntl : input
Connects down to:ff_sre:iu_psr_ice_reg:reset_l , mj_s_ff_snr_d:qual_iu_psr_ice_reg:reset_l , mj_s_ff_snr_d:diag_ld_c_reg:reset_l , mj_s_ff_snr_d:diag_ld_cache_c_reg:reset_l , mj_s_ff_snr_d:valid_diag_c_reg:reset_l , mj_s_ff_s_d:reset_reg:in , mj_s_ff_snr_d:set_stall_reg:reset_l , mj_s_ff_snr_d:nc_fill_cyc_flop:reset_l , mj_s_ff_snr_d:fourth_fill_cyc_flop:reset_l , mj_s_ff_snr_d_6:miss_state_reg:reset_l , mj_s_ff_s_d:miss_state_reg_0:in 
Connects up to:icctl:ic_cntl:reset_l 
 reset_l : ifu : input
Connects down to:ff_sre:flop_gr_1:reset_l , ff_sre:flop_gr_2:reset_l , ff_sre:flop_gr_3:reset_l , ff_sre:flop_gr_4:reset_l , ff_sre:flop_gr_5:reset_l , ff_sre:flop_gr_6:reset_l , ff_sre:flop_gr_7:reset_l , ff_sre:flop_gr_8:reset_l , ff_sre:flop_gr_9:reset_l , ff_sre:flop_fold:reset_l , ff_sre:flop_no_fold:reset_l , ff_sre:flop_valid_rs1:reset_l , ff_sre:flop_help_rs1:reset_l , ff_sre:flop_lv_rs1:reset_l , ff_sre:flop_lv_acc_rs1:reset_l , ff_sre_8:flop_type_rs1:reset_l , ff_sre:flop_rev_ops:reset_l , ff_sre:flop_st_op:reset_l , ff_sre:flop_optop:reset_l , ff_sre:flop_vld_rs2:reset_l , ff_sre:flop_lv_rs2:reset_l , ff_sre:flop_lvars_acc_rs2:reset_l , ff_sre:flop_vld_op_rcu:reset_l , ff_sre:flop_vld_op_ucode:reset_l , ff_sre:flop_vld_op_gen:reset_l , ff_sre_3:flop_offset_br:reset_l , ff_sre:flop_vld_rsd:reset_l , ff_sre:flop_drty_inst:reset_l , ff_sre:flop_putfield:reset_l , mj_spare:spare1:reset_l , mj_spare:spare2:reset_l , ff_sre_3:flop_inst_fold_r:reset_l , ff_sre_3:flop_inst_fold_e:reset_l , ff_sre_3:flop_inst_fold_c:reset_l , ff_sr_3:flop_inst_fold_w:reset_l 
Connects up to:iu:ifu:reset_l 
 reset_l : imdr : input
Connects down to:imdr_ctrl:imdr_ctrl_0:reset_l 
Connects up to:ex:ex_imdr:reset_l 
 reset_l : imdr_ctrl : input
Connects down to:ff_sr:ff_ss_0:reset_l , ff_sr:ff_ss_1:reset_l , ff_sr_4:ff_sr_4_0:reset_l , ff_sr_5:ff_sr_5_0:reset_l , ff_sr_3:ff_sr_3_1:reset_l , ff_sr_3:ff_sr_3_2:reset_l , ff_sr_4:ff_sr_4_1:reset_l , ff_sr_6:ff_sr_6_0:reset_l 
Connects up to:imdr:imdr_ctrl_0:reset_l 
 reset_l : incmod : input
Connects down to:inc_decode:incdec:reset_l , mj_s_ff_snre_d_32:q0reg:reset_l , mj_s_ff_snre_d_32:q1reg:reset_l 
Connects up to:fpu:inc:reset_l 
 reset_l : inc_decode : input
Connects down to:mj_s_ff_snre_d_2:t1mda_ff:reset_l , mj_s_ff_snre_d_2:t0md_ff:reset_l , mj_s_ff_snre_d_2:l0md_ff:reset_l , mj_s_ff_snre_d_2:l1md_ff:reset_l 
Connects up to:incmod:incdec:reset_l 
 reset_l : iu : input
Connects down to:ex:ex:reset_l , ifu:ifu:reset_l , rcu:rcu:reset_l , ucode:ucode:reset_l , pipe:pipe:reset_l , trap:trap:reset_l , hold_logic:hold_logic:reset_l 
Connects up to:cpu:iu:reset_l 
 reset_l : mantissa : input
Connects down to:mantissa_cntl:i_mantissa_cntl:reset_l , mantissa_dp:i_mantissa_dp:reset_l 
Connects up to:fpu:man:reset_l 
 reset_l : mantissa_cntl : input
Connects down to:mj_s_ff_snre_d:a2reg:reset_l 
Connects up to:mantissa:i_mantissa_cntl:reset_l 
 reset_l : mantissa_dp : input
Connects down to:mj_s_ff_snre_d_32:nta1:reset_l , mj_s_ff_snre_d_32:nta0:reset_l , mj_s_ff_snre_d_32:ntb1:reset_l , mj_s_ff_snre_d_32:ntb0:reset_l , mj_s_ff_snre_d_32:ff_r1out:reset_l , mj_s_ff_snre_d_32:ff_r0out:reset_l 
Connects up to:mantissa:i_mantissa_dp:reset_l 
 reset_l : miss_cntl : input
Connects down to:ff_sr_5:miss_state_reg:reset_l , ff_s:miss_state_reg_0:din , ff_sr_5:zero_state_reg:reset_l , ff_s:zero_state_reg_0:din , mj_spare:spare:reset_l 
Connects up to:dcctl:miss_cntl:reset_l 
 reset_l : mj_spare : input
Connects up to:ifu:spare1:reset_l , ifu:spare2:reset_l , ex_ctl:spare1:reset_l , ex_ctl:spare2:reset_l , ucode_seq:spare:reset_l , fpu:i1_spare:reset_l , fpu:i2_spare:reset_l , fpu:i3_spare:reset_l , fpu:i4_spare:reset_l , fpu:i5_spare:reset_l , fpu:i6_spare:reset_l , fpu:i7_spare:reset_l , fpu:i8_spare:reset_l , fpu:i9_spare:reset_l , fpu:i10_spare:reset_l , pipe_cntl:spare:reset_l , miss_cntl:spare:reset_l , dcudp_cntl:spare:reset_l , trap:spare:reset_l , icctl:i1_spare:reset_l , icctl:i2_spare:reset_l , icctl:i3_spare:reset_l , icctl:i4_spare:reset_l , icctl:i5_spare:reset_l , icctl:i6_spare:reset_l , rcu_ctl:spare1:reset_l , rcu_ctl:spare2:reset_l , wrbuf_cntl:spare:reset_l 
 reset_l : mj_s_ff_snre_d : input
Connects up to:ibuf_ctl_slice:valid_flop:reset_l , ibuf_ctl_slice:dirty_flop:reset_l , mj_s_ff_snre_d_12:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d_12:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d_12:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d_12:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d_12:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d_12:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d_12:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d_12:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d_12:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d_12:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d_12:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d_12:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d_16:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d_16:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d_16:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d_16:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d_16:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d_16:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d_16:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d_16:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d_16:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d_16:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d_16:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d_16:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d_16:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d_16:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d_16:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d_16:mj_s_ff_snre_d_15:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_15:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_16:reset_l , mj_s_ff_snre_d_18:mj_s_ff_snre_d_17:reset_l , mj_s_ff_snre_d_2:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d_2:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d_3:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d_3:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d_3:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d_4:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d_4:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d_4:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d_4:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d_6:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d_6:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d_6:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d_6:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d_6:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d_6:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d_7:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d_7:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d_7:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d_7:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d_7:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d_7:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d_7:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d_8:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d_8:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d_8:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d_8:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d_8:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d_8:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d_8:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d_8:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_15:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_16:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_17:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_18:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_19:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_20:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_21:reset_l , mj_s_ff_snre_d_23:mj_s_ff_snre_d_22:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_15:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_16:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_17:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_18:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_19:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_20:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_21:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_22:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_23:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_24:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_25:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_26:reset_l , mj_s_ff_snre_d_28:mj_s_ff_snre_d_27:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_15:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_16:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_17:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_18:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_19:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_20:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_21:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_22:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_23:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_24:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_25:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_26:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_27:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_28:reset_l , mj_s_ff_snre_d_30:mj_s_ff_snre_d_29:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_15:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_16:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_17:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_18:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_19:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_20:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_21:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_22:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_23:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_24:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_25:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_26:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_27:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_28:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_29:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_30:reset_l , mj_s_ff_snre_d_32:mj_s_ff_snre_d_31:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_15:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_16:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_17:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_18:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_19:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_20:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_21:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_22:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_23:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_24:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_25:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_26:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_27:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_28:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_29:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_30:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_31:reset_l , mj_s_ff_snre_d_33:mj_s_ff_snre_d_32:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_15:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_16:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_17:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_18:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_19:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_20:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_21:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_22:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_23:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_24:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_25:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_26:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_27:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_28:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_29:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_30:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_31:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_32:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_33:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_34:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_35:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_36:reset_l , mj_s_ff_snre_d_38:mj_s_ff_snre_d_37:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_15:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_16:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_17:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_18:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_19:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_20:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_21:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_22:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_23:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_24:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_25:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_26:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_27:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_28:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_29:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_30:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_31:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_32:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_33:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_34:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_35:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_36:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_37:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_38:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_39:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_40:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_41:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_42:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_43:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_44:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_45:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_46:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_47:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_48:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_49:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_50:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_51:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_52:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_53:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_54:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_55:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_56:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_57:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_58:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_59:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_60:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_61:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_62:reset_l , mj_s_ff_snre_d_64:mj_s_ff_snre_d_63:reset_l , mantissa_cntl:a2reg:reset_l , nxsign:abs:reset_l , nxsign:abs1:reset_l , nxsign:ead:reset_l , nxsign:absig:reset_l , code_seq_dp:ff_opvalid:reset_l , code_seq_dp:ff_valid:reset_l , code_seq_dp:ff_valid_a:reset_l , ff_sre:mj_s_ff_snre_d_0:reset_l 
 reset_l : mj_s_ff_snre_d_12 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_11:reset_l 
 reset_l : mj_s_ff_snre_d_16 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_15:reset_l 
Connects up to:exponent_dp:ff_excon:reset_l , exponent_dp:aex:reset_l , exponent_dp:bex:reset_l , exponent_dp:sax:reset_l 
 reset_l : mj_s_ff_snre_d_18 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_15:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_16:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_17:reset_l 
Connects up to:multmod_dp:multdecout_moutselcntl:reset_l 
 reset_l : mj_s_ff_snre_d_2 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_1:reset_l 
Connects up to:inc_decode:t1mda_ff:reset_l , inc_decode:t0md_ff:reset_l , inc_decode:l0md_ff:reset_l , inc_decode:l1md_ff:reset_l , mult_array:ffextra6c:reset_l , exptop_dec:mux1ad_ff:reset_l , pri_dec:m1_ff:reset_l 
 reset_l : mj_s_ff_snre_d_23 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_15:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_16:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_17:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_18:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_19:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_20:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_21:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_22:reset_l 
 reset_l : mj_s_ff_snre_d_28 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_15:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_16:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_17:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_18:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_19:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_20:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_21:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_22:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_23:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_24:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_25:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_26:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_27:reset_l 
Connects up to:mult_add:ffincsin:reset_l , multmod_dp:ffsinlo:reset_l , multmod_dp:ffcinlo:reset_l , multmod_dp:ffsinhi:reset_l , multmod_dp:ffcinhi:reset_l 
 reset_l : mj_s_ff_snre_d_3 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_2:reset_l 
Connects up to:rsadd_cntl:ff:reset_l 
 reset_l : mj_s_ff_snre_d_30 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_15:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_16:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_17:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_18:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_19:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_20:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_21:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_22:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_23:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_24:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_25:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_26:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_27:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_28:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_29:reset_l 
 reset_l : mj_s_ff_snre_d_32 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_15:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_16:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_17:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_18:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_19:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_20:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_21:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_22:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_23:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_24:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_25:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_26:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_27:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_28:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_29:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_30:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_31:reset_l 
Connects up to:incmod:q0reg:reset_l , incmod:q1reg:reset_l , mantissa_dp:nta1:reset_l , mantissa_dp:nta0:reset_l , mantissa_dp:ntb1:reset_l , mantissa_dp:ntb0:reset_l , mantissa_dp:ff_r1out:reset_l , mantissa_dp:ff_r0out:reset_l 
 reset_l : mj_s_ff_snre_d_33 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_15:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_16:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_17:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_18:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_19:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_20:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_21:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_22:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_23:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_24:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_25:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_26:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_27:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_28:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_29:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_30:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_31:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_32:reset_l 
 reset_l : mj_s_ff_snre_d_38 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_15:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_16:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_17:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_18:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_19:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_20:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_21:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_22:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_23:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_24:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_25:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_26:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_27:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_28:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_29:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_30:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_31:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_32:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_33:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_34:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_35:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_36:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_37:reset_l 
 reset_l : mj_s_ff_snre_d_4 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_3:reset_l 
Connects up to:code_seq_dp:link_mod:reset_l 
 reset_l : mj_s_ff_snre_d_6 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_5:reset_l 
Connects up to:mult_add:muhold:reset_l , code_seq_cntl:conreg:reset_l , multmod_dp:mult_state:reset_l 
 reset_l : mj_s_ff_snre_d_64 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_7:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_8:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_9:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_10:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_11:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_12:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_13:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_14:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_15:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_16:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_17:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_18:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_19:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_20:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_21:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_22:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_23:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_24:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_25:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_26:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_27:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_28:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_29:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_30:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_31:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_32:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_33:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_34:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_35:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_36:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_37:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_38:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_39:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_40:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_41:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_42:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_43:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_44:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_45:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_46:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_47:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_48:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_49:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_50:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_51:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_52:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_53:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_54:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_55:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_56:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_57:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_58:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_59:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_60:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_61:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_62:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_63:reset_l 
Connects up to:code_seq_dp:mw:reset_l 
 reset_l : mj_s_ff_snre_d_7 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_6:reset_l 
Connects up to:mult_array:ffsavec0:reset_l , mult_array:ffsaves0:reset_l , mult_array:ffsaves1:reset_l 
 reset_l : mj_s_ff_snre_d_8 : input
Connects down to:mj_s_ff_snre_d:mj_s_ff_snre_d_0:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_1:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_2:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_3:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_4:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_5:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_6:reset_l , mj_s_ff_snre_d:mj_s_ff_snre_d_7:reset_l 
Connects up to:fpu_dec:ff_fpstate:reset_l , code_seq_dp:ffopcode:reset_l 
 reset_l : mj_s_ff_snr_d : input
Connects up to:mj_s_ff_snr_d_20:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d_20:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d_21:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d_22:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d_23:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d_24:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d_25:mj_s_ff_snr_d_24:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_24:reset_l , mj_s_ff_snr_d_26:mj_s_ff_snr_d_25:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_24:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_25:reset_l , mj_s_ff_snr_d_27:mj_s_ff_snr_d_26:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_24:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_25:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_26:reset_l , mj_s_ff_snr_d_28:mj_s_ff_snr_d_27:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_24:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_25:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_26:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_27:reset_l , mj_s_ff_snr_d_29:mj_s_ff_snr_d_28:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_24:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_25:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_26:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_27:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_28:reset_l , mj_s_ff_snr_d_30:mj_s_ff_snr_d_29:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_24:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_25:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_26:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_27:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_28:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_29:reset_l , mj_s_ff_snr_d_31:mj_s_ff_snr_d_30:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_24:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_25:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_26:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_27:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_28:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_29:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_30:reset_l , mj_s_ff_snr_d_32:mj_s_ff_snr_d_31:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_24:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_25:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_26:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_27:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_28:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_29:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_30:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_31:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_32:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_33:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_34:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_35:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_36:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_37:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_38:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_39:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_40:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_41:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_42:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_43:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_44:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_45:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_46:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_47:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_48:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_49:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_50:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_51:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_52:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_53:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_54:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_55:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_56:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_57:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_58:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_59:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_60:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_61:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_62:reset_l , mj_s_ff_snr_d_64:mj_s_ff_snr_d_63:reset_l , mj_s_ff_snr_d_2:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_2:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_3:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_3:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_3:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_4:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_4:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_4:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_4:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_5:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_5:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_5:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_5:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_5:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_6:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_6:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_6:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_6:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_6:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_6:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_7:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_7:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_7:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_7:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_7:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_7:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_7:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_8:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_8:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_8:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_8:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_8:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_8:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_8:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_8:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_9:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_9:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_9:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_9:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_9:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_9:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_9:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_9:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_9:mj_s_ff_snr_d_8:reset_l , icu_dpath:misc_wrd_se_reg:reset_l , ff_sr:mj_s_ff_snr_d_0:reset_l , code_seq_dp:tbe:reset_l , ic_cntl:qual_iu_psr_ice_reg:reset_l , ic_cntl:diag_ld_c_reg:reset_l , ic_cntl:diag_ld_cache_c_reg:reset_l , ic_cntl:valid_diag_c_reg:reset_l , ic_cntl:set_stall_reg:reset_l , ic_cntl:nc_fill_cyc_flop:reset_l , ic_cntl:fourth_fill_cyc_flop:reset_l , mj_s_ff_snr_d_10:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_10:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_10:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_10:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_10:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_10:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_10:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_10:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_10:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_10:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_11:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_11:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_11:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_11:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_11:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_11:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_11:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_11:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_11:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_11:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_11:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_12:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_12:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_12:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_12:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_12:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_12:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_12:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_12:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_12:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_12:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_12:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_12:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_13:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_13:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_13:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_13:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_13:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_13:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_13:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_13:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_13:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_13:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_13:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_13:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_13:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_14:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_14:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_14:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_14:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_14:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_14:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_14:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_14:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_14:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_14:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_14:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_14:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_14:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_14:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_15:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_15:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_15:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_15:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_15:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_15:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_15:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_15:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_15:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_15:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_15:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_15:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_15:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_15:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_15:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_16:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_16:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_16:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_16:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_16:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_16:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_16:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_16:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_16:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_16:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_16:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_16:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_16:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_16:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_16:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_16:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_17:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_17:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_17:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_17:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_17:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_17:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_17:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_17:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_17:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_17:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_17:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_17:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_17:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_17:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_17:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_17:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_17:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d_18:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d_19:mj_s_ff_snr_d_18:reset_l 
 reset_l : mj_s_ff_snr_d_10 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l 
 reset_l : mj_s_ff_snr_d_11 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l 
 reset_l : mj_s_ff_snr_d_12 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l 
 reset_l : mj_s_ff_snr_d_13 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l 
 reset_l : mj_s_ff_snr_d_14 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l 
 reset_l : mj_s_ff_snr_d_15 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l 
 reset_l : mj_s_ff_snr_d_16 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l 
 reset_l : mj_s_ff_snr_d_17 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_16:reset_l 
 reset_l : mj_s_ff_snr_d_18 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_17:reset_l 
 reset_l : mj_s_ff_snr_d_19 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_18:reset_l 
 reset_l : mj_s_ff_snr_d_2 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l 
 reset_l : mj_s_ff_snr_d_20 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_19:reset_l 
 reset_l : mj_s_ff_snr_d_21 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_20:reset_l 
 reset_l : mj_s_ff_snr_d_22 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_21:reset_l 
 reset_l : mj_s_ff_snr_d_23 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_22:reset_l 
 reset_l : mj_s_ff_snr_d_24 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_23:reset_l 
 reset_l : mj_s_ff_snr_d_25 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_24:reset_l 
 reset_l : mj_s_ff_snr_d_26 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_24:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_25:reset_l 
 reset_l : mj_s_ff_snr_d_27 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_24:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_25:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_26:reset_l 
 reset_l : mj_s_ff_snr_d_28 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_24:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_25:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_26:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_27:reset_l 
 reset_l : mj_s_ff_snr_d_29 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_24:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_25:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_26:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_27:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_28:reset_l 
 reset_l : mj_s_ff_snr_d_3 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l 
 reset_l : mj_s_ff_snr_d_30 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_24:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_25:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_26:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_27:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_28:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_29:reset_l 
 reset_l : mj_s_ff_snr_d_31 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_24:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_25:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_26:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_27:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_28:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_29:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_30:reset_l 
 reset_l : mj_s_ff_snr_d_32 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_24:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_25:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_26:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_27:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_28:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_29:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_30:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_31:reset_l 
Connects up to:ibuffer:jmp_pc_d1_reg:reset_l , ibuffer:pc_flop:reset_l 
 reset_l : mj_s_ff_snr_d_4 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l 
 reset_l : mj_s_ff_snr_d_5 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l 
 reset_l : mj_s_ff_snr_d_6 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l 
Connects up to:ic_cntl:miss_state_reg:reset_l 
 reset_l : mj_s_ff_snr_d_64 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_9:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_10:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_11:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_12:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_13:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_14:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_15:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_16:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_17:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_18:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_19:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_20:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_21:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_22:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_23:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_24:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_25:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_26:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_27:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_28:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_29:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_30:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_31:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_32:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_33:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_34:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_35:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_36:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_37:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_38:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_39:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_40:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_41:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_42:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_43:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_44:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_45:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_46:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_47:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_48:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_49:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_50:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_51:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_52:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_53:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_54:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_55:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_56:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_57:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_58:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_59:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_60:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_61:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_62:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_63:reset_l 
 reset_l : mj_s_ff_snr_d_7 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l 
 reset_l : mj_s_ff_snr_d_8 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l 
Connects up to:code_seq_dp:tba:reset_l , ibuf_ctl:iu_shift_e_reg:reset_l 
 reset_l : mj_s_ff_snr_d_9 : input
Connects down to:mj_s_ff_snr_d:mj_s_ff_snr_d_0:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_1:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_2:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_3:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_4:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_5:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_6:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_7:reset_l , mj_s_ff_snr_d:mj_s_ff_snr_d_8:reset_l 
 reset_l : monitor : wire
Connects down to:ucode_monitor:ucode_monitor:reset_l 
 reset_l : multmod : input
Connects down to:multmod_dp:p_multmod_dp:reset_l , multmod_cntl:p_multmod_cntl:reset_l 
Connects up to:fpu:mult1:reset_l 
 reset_l : multmod_cntl : input
Connects up to:multmod:p_multmod_cntl:reset_l 
 reset_l : multmod_dp : input
Connects down to:mj_s_ff_snre_d_18:multdecout_moutselcntl:reset_l , mj_s_ff_snre_d_28:ffsinlo:reset_l , mj_s_ff_snre_d_28:ffcinlo:reset_l , mj_s_ff_snre_d_28:ffsinhi:reset_l , mj_s_ff_snre_d_28:ffcinhi:reset_l , mult_array:marray:reset_l , mult_add:madd:reset_l , mj_s_ff_snre_d_6:mult_state:reset_l 
Connects up to:multmod:p_multmod_dp:reset_l 
 reset_l : mult_add : input
Connects down to:mj_s_ff_snre_d_28:ffincsin:reset_l , mj_s_ff_snre_d_6:muhold:reset_l 
Connects up to:multmod_dp:madd:reset_l 
 reset_l : mult_array : input
Connects down to:mj_s_ff_snre_d_7:ffsavec0:reset_l , mj_s_ff_snre_d_7:ffsaves0:reset_l , mj_s_ff_snre_d_7:ffsaves1:reset_l , mj_s_ff_snre_d_2:ffextra6c:reset_l 
Connects up to:multmod_dp:marray:reset_l 
 reset_l : nxsign : input
Connects down to:mj_s_ff_snre_d:abs:reset_l , mj_s_ff_snre_d:abs1:reset_l , mj_s_ff_snre_d:ead:reset_l , mj_s_ff_snre_d:absig:reset_l 
Connects up to:fpu:nxs:reset_l 
 reset_l : pcsu : input
Connects down to:ff_sr_2:pcsu_reg_2_1:reset_l , ff_s:pcsu_reg_0:din 
Connects up to:cpu:pcsu:reset_l 
 reset_l : pipe : input
Connects down to:pipe_dpath:pipe_dpath:reset_l , pipe_cntl:pipe_cntl:reset_l 
Connects up to:iu:pipe:reset_l 
 reset_l : pipe_cntl : input
Connects down to:ff_sre:vld_e_reg:reset_l , ff_sre:vld_e_v1_reg:reset_l , ff_sre:vld_c_reg:reset_l , ff_sr:vld_w_reg:reset_l , ff_sre:flop_bypass_rs1_hit:reset_l , ff_sre:flop_bypass_rs2_hit:reset_l , ff_sr_3:smiss_state_reg:reset_l , ff_sr:hold_e_reg:reset_l , ff_sr:kill_dv_reg:reset_l , ff_sr_3:lduse_state_reg:reset_l , ff_sr:iu_perf_reg:reset_l , ff_sre:ucode_done_reg:reset_l , ff_sre:fold_e_reg:reset_l , ff_sre:fold_c_reg:reset_l , ff_sr:sc_sticky_reg:reset_l , ff_sre:fold_sc_reg:reset_l , ff_sr:fold_trapped_reg:reset_l , ff_sr_4:fold_state_reg:reset_l , ff_s:fold_state_reg_0:din , mj_spare:spare:reset_l 
Connects up to:pipe:pipe_cntl:reset_l 
 reset_l : pipe_dpath : input
Connects down to:ff_sre_32:arch_pcreg:reset_l 
Connects up to:pipe:pipe_dpath:reset_l 
 reset_l : prils : input
Connects down to:prils_cntl:i_prils_cntl:reset_l 
Connects up to:fpu:prif:reset_l 
 reset_l : prils_cntl : input
Connects down to:pri_dec:prid:reset_l 
Connects up to:prils:i_prils_cntl:reset_l 
 reset_l : pri_dec : input
Connects down to:mj_s_ff_snre_d_2:m1_ff:reset_l 
Connects up to:prils_cntl:prid:reset_l 
 reset_l : rcu : input
Connects down to:rcu_ctl:rcu_ctl:reset_l 
Connects up to:iu:rcu:reset_l 
 reset_l : rcu_ctl : input
Connects down to:ff_sr:flop_scache_hit:reset_l , ff_sre:flop_data_we_e:reset_l , ff_sre:flop_data_we_c:reset_l , ff_sr:flop_data_we_w:reset_l , ff_sr:flop_scache_wr_miss:reset_l , ff_sre:flop_global_we_e:reset_l , ff_sre:flop_global_we_c:reset_l , ff_sr:flop_global_we_w:reset_l , ff_sr:flop_mult_cyc_st:reset_l , ff_s:flop_mult_cyc_st_0:din , ff_sre:flop_fc_e:reset_l , ff_sre:flop_fc_c:reset_l , ff_sr:flop_fc_w:reset_l , ff_sre:flop_udone_c:reset_l , ff_sre:flop_udone_w:reset_l , mj_spare:spare1:reset_l , mj_spare:spare2:reset_l 
Connects up to:rcu:rcu_ctl:reset_l 
 reset_l : rsadd : input
Connects down to:rsadd_cntl:p_rsadd_cntl:reset_l 
Connects up to:fpu:rsa:reset_l 
 reset_l : rsadd_cntl : input
Connects down to:mj_s_ff_snre_d_3:ff:reset_l 
Connects up to:rsadd:p_rsadd_cntl:reset_l 
 reset_l : smu : input
Connects down to:smu_ctl:smu_ctl:reset_l 
Connects up to:cpu:smu:reset_l 
 reset_l : smu_ctl : input
Connects down to:ff_sr:spill_flop:reset_l , ff_sr_3:cs_spill_reg:reset_l , ff_s:cs_spill_reg0:din , ff_sr:fill_flop:reset_l , ff_sr:ovr_flw_flop:reset_l , ff_sr:und_flw_flop:reset_l , ff_sr:flush_flop:reset_l , ff_sr:int_flop:reset_l , ff_sre:load_c_flop:reset_l , ff_sr:load_w_flop:reset_l , ff_sre:store_c_flop:reset_l , ff_sr:store_w_flop:reset_l , ff_sr:delay_flop1:reset_l , ff_sr:delay_flop2:reset_l , ff_sr:iu_smiss_flop:reset_l , ff_sr:squash_flop1:reset_l , ff_sr:squash_flop2:reset_l , ff_sr:squash_flop3:reset_l , ff_sr:zero_flop:reset_l , ff_sr:idle_flop:reset_l , ff_sr:smu_prty_flop:reset_l , ff_sr:squash_flop:reset_l , ff_sr_4:dribb_state_reg:reset_l , ff_s:dribb_state_reg_0:din , ff_sr:six_state_reg:reset_l , ff_s:six_state_reg_0:din 
Connects up to:smu:smu_ctl:reset_l 
 reset_l : trap : input
Connects down to:ff_sre:irl_r_reg:reset_l , ff_sre:irl_e_reg:reset_l , ff_sre:irl_c_reg:reset_l , ff_sre_4:pj_irl_r_reg:reset_l , ff_sre_4:pj_irl_e_reg:reset_l , ff_sre_4:pj_irl_c_reg:reset_l , ff_sre:nmi_r_reg:reset_l , ff_sre:nmi_e_reg:reset_l , ff_sre:nmi_c_reg:reset_l , ff_sre:inst_brk1_e_reg:reset_l , ff_sre:inst_brk2_e_reg:reset_l , ff_sre:inst_brk1_c_reg:reset_l , ff_sre:inst_brk2_c_reg:reset_l , ff_sre:first_cyc_c_reg:reset_l , ff_sre:imem_e_reg:reset_l , ff_sre:imem_c_reg:reset_l , ff_sre:ill_e_reg:reset_l , ff_sre:ill_c_reg:reset_l , ff_sre:priv_e_reg:reset_l , ff_sre:priv_c_reg:reset_l , ff_sre:fpu_e_reg:reset_l , ff_sre:fpu_c_reg:reset_l , ff_sre:emul_op_e_reg:reset_l , ff_sre:emul_op_c_reg:reset_l , ff_sre:soft_e_reg:reset_l , ff_sre:soft_c_reg:reset_l , ff_sre_4:lock_trap_reg:reset_l , ff_sre:zero_c_reg:reset_l , ff_sre:vm_err_c_reg:reset_l , ff_sre:null_ptr_c_reg:reset_l , ff_sr:async_err_reg:reset_l , ff_sr:br_c_reg:reset_l , ff_sre:trap_vld_e_reg:reset_l , ff_sre:trap_vld_c_reg:reset_l , ff_sr:trap_stat_reg:reset_l , ff_sre:iu_trap_reg:reset_l , ff_sre:trap_w_reg:reset_l , ff_sre:brtaken_reg:reset_l , mj_spare:spare:reset_l 
Connects up to:iu:trap:reset_l 
 reset_l : ucode : input
Connects down to:ucode_ctrl:ucode_ctrl_0:reset_l , ucode_dpath:ucode_dpath_0:reset_l 
Connects up to:iu:ucode:reset_l 
 reset_l : ucode_ctrl : input
Connects down to:ucode_ind:ucode_ind_0:reset_l , ucode_seq:ucode_seq_0:reset_l 
Connects up to:ucode:ucode_ctrl_0:reset_l 
 reset_l : ucode_dat : input
Connects up to:ucode_dpath:ucode_dat_0:reset_l 
 reset_l : ucode_dpath : input
Connects down to:ucode_dat:ucode_dat_0:reset_l 
Connects up to:ucode:ucode_dpath_0:reset_l 
 reset_l : ucode_ind : input
Connects down to:ff_sre_16:ff_sre_16_1:reset_l 
Connects up to:ucode_ctrl:ucode_ind_0:reset_l 
 reset_l : ucode_monitor : input
Connects down to:ff_sre:reset_l_minus_1:din , ff_sre:reset_l_minus_1:reset_l , ff_sre:reset_l_minus_2:reset_l , ff_sre:reset_l_minus_3:reset_l , ff_sre:invoke_e_flop:reset_l 
Connects up to:monitor:ucode_monitor:reset_l , monitor:ucode_monitor:biu 
 reset_l : ucode_seq : input
Connects down to:mj_spare:spare:reset_l 
Connects up to:ucode_ctrl:ucode_seq_0:reset_l 
 reset_l : wrbuf_cntl : input
Connects down to:ff_sr:repl_state_reg0:reset_l , ff_sr:repl_state_reg1:reset_l , ff_sr_7:wb_state_reg:reset_l , ff_s:wb_state_reg_0:din , mj_spare:spare:reset_l 
Connects up to:dcctl:wrbuf_cntl:reset_l 
 reset_l_1 : ucode_monitor : wire
Connects down to:ff_sre:reset_l_minus_1:out , ff_sre:reset_l_minus_2:din 
 reset_l_2 : ucode_monitor : wire
Connects down to:ff_sre:reset_l_minus_2:out , ff_sre:reset_l_minus_3:din 
 reset_l_3 : ucode_monitor : wire
Connects down to:ff_sre:reset_l_minus_3:out 
 reset_out : iu : output wire
Connects down to:ex:ex:priv_reset_e 
Connects up to:cpu:iu:pj_reset_out 
 result : comp30_6 : output
Connects up to:smu_ctl:fill_comp:fill_raw 
 result : comp3_30 : output
Connects up to:smu_ctl:six_entr_comp:less_than_6_raw 
 result : comp6_30 : output
Connects up to:smu_ctl:spill_comp:spill_raw , smu_ctl:ovr_fl_cmp:ovr_flw_bit 
 result : inc_dec_30 : output
Connects down to:cla_adder_32:adder:sum 
Connects up to:smu_dpath:inc_dec:sbase_c_inc_dec_out 
 result : shift_64 : wire
Connects down to:mx21_64_l:mx_7:mx_out 
 result : sub2_32 : output
Connects down to:cla_adder_32:adder:sum 
Connects up to:smu_dpath:sub:num_entries_out 
 ret : ex_ctl : wire
Connects down to:ff_sre:ret_e_flop:din 
 ret : rs1_dec : reg
 ret : rs2_dec : wire
 return : ex_ctl : wire
 return0 : ex_ctl : wire
 return1 : ex_ctl : wire
 return2 : ex_ctl : wire
 return_code : picoJavaII : reg
 ret_e : ex_ctl : wire
Connects down to:ff_sre:ret_e_flop:out 
 ret_optop_update : cpu : wire
Connects down to:iu:iu:ret_optop_update , smu:smu:ret_optop_update 
 ret_optop_update : ex : output
Connects down to:ex_ctl:ex_ctl:ret_optop_update 
Connects up to:iu:ex:ret_optop_update 
 ret_optop_update : ex_ctl : output
Connects down to:ff_sr:ret_optop_update_flop:out 
Connects up to:ex:ex_ctl:ret_optop_update 
 ret_optop_update : iu : output wire
Connects down to:ex:ex:ret_optop_update 
Connects up to:cpu:iu:ret_optop_update 
 ret_optop_update : smu : input
Connects down to:smu_ctl:smu_ctl:ret_optop_update 
Connects up to:cpu:smu:ret_optop_update 
 ret_optop_update : smu_ctl : input
Connects down to:ff_sr:squash_flop1:din 
Connects up to:smu:smu_ctl:ret_optop_update 
 ret_optop_update_e : ex_ctl : wire
Connects down to:ff_sr:ret_optop_update_flop:din 
 reverse_ops : rs1_dec : output
Connects up to:main_dec:rs1_dec:reverse_ops_rs1 
 reverse_ops_rs1 : ifu : wire
Connects down to:main_dec:main_dec:reverse_ops_rs1 , ff_sre:flop_rev_ops:din 
 reverse_ops_rs1 : main_dec : output
Connects down to:rs1_dec:rs1_dec:reverse_ops 
Connects up to:ifu:main_dec:reverse_ops_rs1 
 reverse_ops_rs1_r : ifu : output
Connects down to:ff_sre:flop_rev_ops:out 
Connects up to:iu:ifu:reverse_ops_rs1_r 
 reverse_ops_rs1_r : iu : wire
Connects down to:ifu:ifu:reverse_ops_rs1_r , rcu:rcu:reverse_ops_rs1_r 
 reverse_ops_rs1_r : rcu : input
Connects down to:rcu_ctl:rcu_ctl:reverse_ops_rs1_r 
Connects up to:iu:rcu:reverse_ops_rs1_r 
 reverse_ops_rs1_r : rcu_ctl : input
Connects up to:rcu:rcu_ctl:reverse_ops_rs1_r 
 rev_lev_6 : shift_64 : wire
Connects down to:mx21_64_l:mx_7:in1 
 rev_sft_in : shift_64 : wire
Connects down to:mx21_64_l:mx_0:in1 
 RI : mppartial : input
Connects up to:mpmux:mppart2:part1lo , mpmux:mppart3:part2lo , mpmux:mppart4:part3lo , mpmux:mppart5:part4lo , mpmux:mppart6:part5lo , mpmux:mppart7:part6lo , mpmux:mppart1:ri_in 
 ri_in : mpmux : wire
Connects down to:mppartial:mppart1:RI 
 rom0out : code_seq_dp : wire
Connects down to:buf_64:buf0:in , fp_roms:fprom_mod:do0 , mj_s_mux3_d_32:romouta:in0 , mj_s_mux3_d_32:romoutb:in0 , acode_dec:acode:nx_a2func_rom0 , mj_s_mux4_d_8:mx_code_add_rom0:in0 , mj_s_mux2_d_4:linkmux_0:in1 
 rom1out : code_seq_dp : wire
Connects down to:buf_64:buf1:in , fp_roms:fprom_mod:do1 , mj_s_mux3_d_32:romouta:in1 , mj_s_mux3_d_32:romoutb:in1 , acode_dec:acode:nx_a2func_rom1 , mj_s_mux4_d_8:mx_code_add_rom1:in0 , mj_s_mux2_d_4:linkmux_1:in1 
 romsel : branch_dec : output
Connects down to:mj_s_mux4_d_2:romsel_mux:mx_out 
Connects up to:code_seq_cntl:branchd:romsel 
 romsel : code_seq : output
Connects down to:code_seq_cntl:p_code_seq_cntl:romsel , code_seq_dp:p_code_seq_dp:romsel 
Connects up to:fpu:cs:romsel 
 romsel : code_seq_cntl : output
Connects down to:branch_dec:branchd:romsel 
Connects up to:code_seq:p_code_seq_cntl:romsel 
 romsel : code_seq_dp : input
Connects down to:mj_s_mux3_d_32:romouta:sel , mj_s_mux3_d_32:romoutb:sel , mj_s_mux3_d_8:mx_code_add:sel , mj_s_mux3_d_4:linkmuxfinal:sel 
Connects up to:code_seq:p_code_seq_dp:romsel 
 romsel : exponent : input
Connects down to:exponent_cntl:p_exponent_cntl:romsel , exponent_dp:p_exponent_dp:romsel 
Connects up to:fpu:exp:romsel 
 romsel : exponent_cntl : input
Connects down to:exptop_dec:exptop:romsel 
Connects up to:exponent:p_exponent_cntl:romsel 
 romsel : exponent_dp : input
Connects down to:mj_s_mux3_d_16:excon_mux:sel 
Connects up to:exponent:p_exponent_dp:romsel 
 romsel : exptop_dec : input
Connects down to:mj_s_mux3_d_2:mux1ad_mux:sel 
Connects up to:exponent_cntl:exptop:romsel 
 romsel : fpu : wire
Connects down to:exponent:exp:romsel , incmod:inc:romsel , prils:prif:romsel , code_seq:cs:romsel , mantissa:man:romsel , multmod:mult1:romsel 
 romsel : incmod : input
Connects down to:inc_decode:incdec:romsel 
Connects up to:fpu:inc:romsel 
 romsel : inc_decode : input
Connects down to:mj_s_mux3_d_2:t1mda_mux:sel , mj_s_mux3_d_2:t0md_mux:sel , mj_s_mux3_d_2:l1md_mux:sel , mj_s_mux3_d_2:l0md_mux:sel 
Connects up to:incmod:incdec:romsel 
 romsel : mantissa : input
Connects down to:mantissa_dp:i_mantissa_dp:romsel 
Connects up to:fpu:man:romsel 
 romsel : mantissa_dp : input
Connects down to:mj_s_mux3_d_32:r0mux:sel , mj_s_mux3_d_32:r1mux:sel 
Connects up to:mantissa:i_mantissa_dp:romsel 
 romsel : multmod : input
Connects down to:multmod_cntl:p_multmod_cntl:romsel 
Connects up to:fpu:mult1:romsel 
 romsel : multmod_cntl : input
Connects down to:mj_s_mux3_d_16:selmultdectop_17_2:sel , mj_s_mux3_d_2:selmultdec_1_0:sel 
Connects up to:multmod:p_multmod_cntl:romsel 
 romsel : prils : input
Connects down to:prils_cntl:i_prils_cntl:romsel 
Connects up to:fpu:prif:romsel 
 romsel : prils_cntl : input
Connects down to:pri_dec:prid:romsel 
Connects up to:prils:i_prils_cntl:romsel 
 romsel : pri_dec : input
Connects down to:mj_s_mux3_d_2:m1_mux:sel 
Connects up to:prils_cntl:prid:romsel 
 romsel0 : branch_dec : wire
Connects down to:mj_s_mux4_d_2:romsel_mux:in0 
 romsel1 : branch_dec : wire
Connects down to:mj_s_mux4_d_2:romsel_mux:in1 
 romsel2 : branch_dec : wire
Connects down to:mj_s_mux4_d_2:romsel_mux:in2 
 romsel3 : branch_dec : wire
Connects down to:mj_s_mux4_d_2:romsel_mux:in3 
 romselp_a : branch_dec : wire
Connects down to:branch_decode1:b1:romselp_a , mj_s_mux4_d:m1:in1 
 romselp_a : branch_decode1 : output reg
Connects up to:branch_dec:b1:romselp_a 
 romselp_b : branch_dec : wire
Connects down to:branch_decode2:b2:romselp_b , mj_s_mux4_d:m2:in1 
 romselp_b : branch_decode2 : output reg
Connects up to:branch_dec:b2:romselp_b 
 romselp_c : branch_dec : wire
Connects down to:branch_decode3:b3:romselp_c , mj_s_mux4_d:m3:in1 
 romselp_c : branch_decode3 : output reg
Connects up to:branch_dec:b3:romselp_c 
 romselp_d : branch_dec : wire
Connects down to:branch_decode4:b4:romselp_d , mj_s_mux4_d:m4:in1 
 romselp_d : branch_decode4 : output reg
Connects up to:branch_dec:b4:romselp_d 
 romsel_a : branch_dec : wire
Connects down to:mj_s_mux4_d:m1:mx_out 
 romsel_b : branch_dec : wire
Connects down to:mj_s_mux4_d:m2:mx_out 
 romsel_c : branch_dec : wire
Connects down to:mj_s_mux4_d:m3:mx_out 
 romsel_d : branch_dec : wire
Connects down to:mj_s_mux4_d:m4:mx_out 
 rom_addr : ucode : wire
Connects down to:ucode_ctrl:ucode_ctrl_0:rom_addr , ucode_dpath:ucode_dpath_0:nxt_ucode_cnt 
 rom_addr : ucode_add : output wire
Connects down to:ucode_dec:ucode_dec_0:rom_addr 
Connects up to:ucode_ctrl:ucode_add_0:rom_addr 
 rom_addr : ucode_ctrl : output wire
Connects down to:ucode_add:ucode_add_0:rom_addr 
Connects up to:ucode:ucode_ctrl_0:rom_addr 
 rom_addr : ucode_dec : output wire
Connects up to:ucode_add:ucode_dec_0:rom_addr 
 rom_addr_1 : ucode_seq : wire
Connects down to:inc9:inc9_rom_add1:sum , ff_sre_9:seq_addr1_reg:din 
 rom_addr_2 : ucode_seq : wire
Connects down to:inc8:inc8_rom_add2:sum , ff_sre_9:seq_addr2_reg:din 
 rom_addr_3 : ucode_seq : wire
Connects down to:fa9:fa9_rom_add3:sum , ff_sre_9:seq_addr3_reg:din 
 rom_addr_l : ucode_add : output wire
Connects up to:ucode_ctrl:ucode_add_0:rom_addr_l 
 rom_addr_l : ucode_ctrl : wire
Connects down to:ucode_add:ucode_add_0:rom_addr_l , ucode_seq:ucode_seq_0:rom_addr_l 
 rom_addr_l : ucode_seq : input
Connects up to:ucode_ctrl:ucode_seq_0:rom_addr_l 
 rom_data : ieu_rom : output reg
Connects up to:ucode_dpath:ieu_rom_0:rom_data 
 rom_data : ucode_dpath : wire
Connects down to:ieu_rom:ieu_rom_0:rom_data , ucode_reg:ucode_reg_0:rom_fxx 
 rom_en : fp_roms : input
Connects up to:code_seq_dp:fprom_mod:fpuhold_l 
 rom_fxx : ucode_reg : input
Connects up to:ucode_dpath:ucode_reg_0:rom_data 
 rom_fxx : ucode_rom : output wire
 rom_mux_out : code_seq_dp : wire
Connects down to:mj_s_mux3_d_32:romouta:mx_out , mj_s_mux3_d_32:romoutb:mx_out , mj_s_ff_snre_d_64:mw:din 
 rom_start : ucode_dec : reg
 rom_start_r : ucode_dec : wire
 roundout : prils_round_dec : output
Connects up to:prils_dp:ls2:lsround 
 roundout : round_dec : output
Connects up to:rsadd_cntl:rs2:rsround 
 row0c_bit : mult_array : wire
Connects down to:tree27:treerow0:co , propagate_end:propend:row0c_bit3 
 row0c_bit3 : propagate_end : input
Connects down to:multadd2:triangle1:bi 
Connects up to:mult_array:propend:row0c_bit 
 row0s_bit : mult_array : wire
Connects down to:tree27:treerow0:so , propagate_end:propend:row0s_bit3 , propagate_end:propend:row0s_bit2 
 row0s_bit2 : propagate_end : input
Connects down to:multadd2:triangle1:ai 
Connects up to:mult_array:propend:row0s_bit 
 row0s_bit3 : propagate_end : input
Connects down to:multadd2:triangle1:ai 
Connects up to:mult_array:propend:row0s_bit 
 row1c_bit : mult_array : wire
Connects down to:tree23:treerow1:co , guesscout:guesscout0:row1c_bit14 
 row1c_bit14 : guesscout : input
Connects down to:multfa:guessfa0:ai 
Connects up to:mult_array:guesscout0:row1c_bit 
 row1s_bit : mult_array : wire
Connects down to:tree23:treerow1:so 
 row2c_bit : mult_array : wire
Connects down to:tree23:treerow2:co 
 row2s_bit : mult_array : wire
Connects down to:tree23:treerow2:so , guesscout:guesscout0:row2s_bit14 
 row2s_bit14 : guesscout : input
Connects down to:multfa:guessfa0:bi 
Connects up to:mult_array:guesscout0:row2s_bit 
 row3c_bit : mult_array : wire
Connects down to:tree29:treerow3:co , guesscout:guesscout0:row3c_bit14 , propagate_end:propend:row3c_bit5 , propagate_end:propend:row3c_bit8 
 row3c_bit14 : guesscout : input
Connects down to:multfa:guessfa1:bi 
Connects up to:mult_array:guesscout0:row3c_bit 
 row3c_bit5 : propagate_end : input
Connects down to:multadd2:triangle2:bi 
Connects up to:mult_array:propend:row3c_bit 
 row3c_bit8 : propagate_end : input
Connects down to:multfa:propfa0:ai 
Connects up to:mult_array:propend:row3c_bit 
 row3s_bit : mult_array : wire
Connects down to:tree29:treerow3:so , guesscout:guesscout0:row3s_bit14 , propagate_end:propend:row3s_bit5 , propagate_end:propend:row3s_bit4 , propagate_end:propend:row3s_bit8 
 row3s_bit14 : guesscout : input
Connects down to:multfa:guessfa1:ai 
Connects up to:mult_array:guesscout0:row3s_bit 
 row3s_bit4 : propagate_end : input
Connects down to:multadd2:triangle2:ai 
Connects up to:mult_array:propend:row3s_bit 
 row3s_bit5 : propagate_end : input
Connects down to:multadd2:triangle2:ai 
Connects up to:mult_array:propend:row3s_bit 
 row3s_bit8 : propagate_end : input
Connects down to:multfa:propfa0:bi 
Connects up to:mult_array:propend:row3s_bit 
 row4c_bit : mult_array : wire
Connects down to:tree29:treerow4:co , tree34:treerow5:bi , tree34:treerow6:ci , tree34:treerow6:ci , guesscout:guesscout0:row4c_bit14 
 row4c_bit14 : guesscout : input
Connects down to:multfa:guessfa2:bi 
Connects up to:mult_array:guesscout0:row4c_bit 
 row4s_bit : mult_array : wire
Connects down to:tree29:treerow4:so , tree34:treerow5:ci 
 row5c_bit : mult_array : wire
Connects down to:tree34:treerow5:co , guesscout:guesscout0:row5c_bit14 , propagate_end:propend:row5c_bit7 , propagate_end:propend:row5c_bit8 , propagate_end:propend:row5c_bit12 
 row5c_bit12 : propagate_end : input
Connects down to:multfa:propfa3:ai 
Connects up to:mult_array:propend:row5c_bit 
 row5c_bit14 : guesscout : input
Connects down to:multfa:guessfa2:ai 
Connects up to:mult_array:guesscout0:row5c_bit 
 row5c_bit7 : propagate_end : input
Connects down to:multadd2:triangle3:bi 
Connects up to:mult_array:propend:row5c_bit 
 row5c_bit8 : propagate_end : input
Connects down to:multfa:propfa1:bi 
Connects up to:mult_array:propend:row5c_bit 
 row5s_bit : mult_array : wire
Connects down to:tree34:treerow5:so , guesscout:guesscout0:row5s_bit15 , propagate_end:propend:row5s_bit7 , propagate_end:propend:row5s_bit6 , propagate_end:propend:row5s_bit9 , propagate_end:propend:row5s_bit12 
 row5s_bit12 : propagate_end : input
Connects down to:multfa:propfa3:bi 
Connects up to:mult_array:propend:row5s_bit 
 row5s_bit15 : guesscout : input
Connects down to:multfa:guessfa3:ai 
Connects up to:mult_array:guesscout0:row5s_bit 
 row5s_bit6 : propagate_end : input
Connects down to:multadd2:triangle3:ai 
Connects up to:mult_array:propend:row5s_bit 
 row5s_bit7 : propagate_end : input
Connects down to:multadd2:triangle3:ai 
Connects up to:mult_array:propend:row5s_bit 
 row5s_bit9 : propagate_end : input
Connects down to:multfa:propfa2:bi 
Connects up to:mult_array:propend:row5s_bit 
 row6c_bit : mult_array : wire
Connects down to:tree34:treerow6:co , guesscout:guesscout0:row6c_bit14 , guesscout:guesscout0:row6c_bit15 , guesscout:guesscout0:row6c_bit16 , mj_s_ff_snre_d_7:ffsavec0:din , mj_s_ff_snre_d_2:ffextra6c:din , propagate_end:propend:row6c_bit12 , propagate_end:propend:row6c_bit11 
 row6c_bit11 : propagate_end : input
Connects down to:fa6:last_part:b 
Connects up to:mult_array:propend:row6c_bit 
 row6c_bit12 : propagate_end : input
Connects down to:fa6:last_part:b 
Connects up to:mult_array:propend:row6c_bit 
 row6c_bit14 : guesscout : input
Connects down to:mj_s_mux2_d_4:guessfinal0:sel 
Connects up to:mult_array:guesscout0:row6c_bit 
 row6c_bit15 : guesscout : input
Connects down to:mj_s_mux2_d_4:guessfinal0:in0 
Connects up to:mult_array:guesscout0:row6c_bit 
 row6c_bit16 : guesscout : input
Connects down to:mj_s_mux2_d_4:guessfinal0:in0 
Connects up to:mult_array:guesscout0:row6c_bit 
 row6s_bit : mult_array : wire
Connects down to:tree34:treerow6:so , guesscout:guesscout0:row6s_bit14 , guesscout:guesscout0:row6s_bit15 , mj_s_ff_snre_d_7:ffsaves0:din , mj_s_ff_snre_d_7:ffsaves1:din , propagate_end:propend:row6s_bit13 , propagate_end:propend:row6s_bit11 , propagate_end:propend:row6s_bit10 
 row6s_bit10 : propagate_end : input
Connects down to:fa6:last_part:a 
Connects up to:mult_array:propend:row6s_bit 
 row6s_bit11 : propagate_end : input
Connects down to:fa6:last_part:a 
Connects up to:mult_array:propend:row6s_bit 
 row6s_bit13 : propagate_end : input
Connects down to:fa6:last_part:a 
Connects up to:mult_array:propend:row6s_bit 
 row6s_bit14 : guesscout : input
Connects down to:mj_s_mux2_d_4:guessfinal0:in0 
Connects up to:mult_array:guesscout0:row6s_bit 
 row6s_bit15 : guesscout : input
Connects down to:mj_s_mux2_d_4:guessfinal0:in0 
Connects up to:mult_array:guesscout0:row6s_bit 
 rr512x5_ENABLE : Controller1 : output
Connects up to:dtag_top:Controller_Ins:rr512x5_ENABLE 
 rr512x5_ENABLE : dtag_top : wire
Connects down to:Controller1:Controller_Ins:rr512x5_ENABLE , rr512x5_LocalBist:rr512x5_Bist_Ins:rr512x5_ENABLE 
 rr512x5_ENABLE : rr512x5_LocalBist : input
Connects up to:dtag_top:rr512x5_Bist_Ins:rr512x5_ENABLE 
 rr512x5_ERROR : Controller1 : input
Connects up to:dtag_top:Controller_Ins:rr512x5_ERROR 
 rr512x5_ERROR : dtag_top : wire
Connects down to:Controller1:Controller_Ins:rr512x5_ERROR , rr512x5_LocalBist:rr512x5_Bist_Ins:rr512x5_ERROR 
 rr512x5_ERROR : rr512x5_LocalBist : output
Connects up to:dtag_top:rr512x5_Bist_Ins:rr512x5_ERROR 
 rrdtag_0_ENABLE : Controller1 : output
Connects up to:dtag_top:Controller_Ins:rrdtag_0_ENABLE 
 rrdtag_0_ENABLE : dtag_top : wire
Connects down to:Controller1:Controller_Ins:rrdtag_0_ENABLE , rrdtag_0_LocalBist:rrdtag_0_Bist_Ins:rrdtag_0_ENABLE 
 rrdtag_0_ENABLE : rrdtag_0_LocalBist : input
Connects up to:dtag_top:rrdtag_0_Bist_Ins:rrdtag_0_ENABLE 
 rrdtag_0_ERROR : Controller1 : input
Connects up to:dtag_top:Controller_Ins:rrdtag_0_ERROR 
 rrdtag_0_ERROR : dtag_top : wire
Connects down to:Controller1:Controller_Ins:rrdtag_0_ERROR , rrdtag_0_LocalBist:rrdtag_0_Bist_Ins:rrdtag_0_ERROR 
 rrdtag_0_ERROR : rrdtag_0_LocalBist : output
Connects up to:dtag_top:rrdtag_0_Bist_Ins:rrdtag_0_ERROR 
 rrdtag_1_ENABLE : Controller1 : output
Connects up to:dtag_top:Controller_Ins:rrdtag_1_ENABLE 
 rrdtag_1_ENABLE : dtag_top : wire
Connects down to:Controller1:Controller_Ins:rrdtag_1_ENABLE , rrdtag_1_LocalBist:rrdtag_1_Bist_Ins:rrdtag_1_ENABLE 
 rrdtag_1_ENABLE : rrdtag_1_LocalBist : input
Connects up to:dtag_top:rrdtag_1_Bist_Ins:rrdtag_1_ENABLE 
 rrdtag_1_ERROR : Controller1 : input
Connects up to:dtag_top:Controller_Ins:rrdtag_1_ERROR 
 rrdtag_1_ERROR : dtag_top : wire
Connects down to:Controller1:Controller_Ins:rrdtag_1_ERROR , rrdtag_1_LocalBist:rrdtag_1_Bist_Ins:rrdtag_1_ERROR 
 rrdtag_1_ERROR : rrdtag_1_LocalBist : output
Connects up to:dtag_top:rrdtag_1_Bist_Ins:rrdtag_1_ERROR 
 rricache_ERROR : icram_Controller : input
Connects up to:icram_top:Controller_Ins:rricache_ERROR 
 rricache_ERROR : icram_top : wire
Connects down to:icram_Controller:Controller_Ins:rricache_ERROR , rricache_LocalBist:rricache_Bist_Ins:rricache_ERROR 
 rricache_ERROR : rricache_LocalBist : output
Connects up to:icram_top:rricache_Bist_Ins:rricache_ERROR 
 rritag_ERROR : itag_Controller : input
Connects up to:itag_top:Controller_Ins:rritag_ERROR 
 rritag_ERROR : itag_top : wire
Connects down to:itag_Controller:Controller_Ins:rritag_ERROR , rritag_LocalBist:rritag_Bist_Ins:rritag_ERROR 
 rritag_ERROR : rritag_LocalBist : output
Connects up to:itag_top:rritag_Bist_Ins:rritag_ERROR 
 rs1 : ucode : input
Connects down to:inv_a_32:inv_a_32_0:inp , ucode_dpath:ucode_dpath_0:rs1 
Connects up to:iu:ucode:iu_rs1_e 
 rs1 : ucode_dat : input
Connects down to:mj_s_mux8_d_32:mux8_a_oprd:in5 , mj_s_mux8_d_32:mux8_b_oprd:in4 
Connects up to:ucode_dpath:ucode_dat_0:rs1 
 rs1 : ucode_dpath : input
Connects down to:ucode_dat:ucode_dat_0:rs1 
Connects up to:ucode:ucode_dpath_0:rs1_0 , ucode:ucode_dpath_0:rs1 
 rs1_0 : ex_dpath : wire
Connects down to:mux5:rs1_0_bypass_mux:out 
 rs1_0 : ucode : wire
Connects down to:inv_b_1:inv_b_1_0:out_l , ucode_dpath:ucode_dpath_0:rs1 
 rs1_0_l : branch_bit : input
Connects up to:ucode_add:branch_bit_0:rs1_0_l 
 rs1_0_l : ucode : input
Connects down to:inv_b_1:inv_b_1_0:inp , ucode_ctrl:ucode_ctrl_0:rs1_0_l 
Connects up to:iu:ucode:iu_rs1_e_0_l 
 rs1_0_l : ucode_add : input
Connects down to:branch_bit:branch_bit_0:rs1_0_l 
Connects up to:ucode_ctrl:ucode_add_0:rs1_0_l 
 rs1_0_l : ucode_ctrl : input
Connects down to:ucode_add:ucode_add_0:rs1_0_l 
Connects up to:ucode:ucode_ctrl_0:rs1_0_l 
 rs1_0_mux_out : ex_dpath : wire
Connects down to:mux2:rs1_0_mux:out , mux5:rs1_0_bypass_mux:in0 
 rs1_b : ucode : wire
Connects down to:inv_c_32:inv_c_32_0:out_l , ucode_dpath:ucode_dpath_0:rs1_b 
 rs1_b : ucode_dat : input
Connects down to:mj_s_mux6_d_32:mux6_w_mx_a:in2 , mj_s_mux4_d_32:mux4_w_mx_b0:in1 , mj_s_mux4_d_32:mux4_r236:in3 
Connects up to:ucode_dpath:ucode_dat_0:rs1_b 
 rs1_b : ucode_dpath : input
Connects down to:ucode_dat:ucode_dat_0:rs1_b 
Connects up to:ucode:ucode_dpath_0:rs1_b 
 rs1_bypass_hold : ex_dpath : wire
Connects down to:ff_s_32:rs1_bypass_reg:out , mux5_32:rs1_bypass_mux:in4 , mux5:rs1_0_bypass_mux:in4 
 rs1_bypass_hold : iu : wire
Connects down to:ex:ex:rs1_bypass_mux_sel , pipe:pipe:rs1_bypass_hold 
 rs1_bypass_hold : pipe : output
Connects down to:pipe_cntl:pipe_cntl:rs1_bypass_hold 
Connects up to:iu:pipe:rs1_bypass_hold 
 rs1_bypass_hold : pipe_cntl : output
Connects up to:pipe:pipe_cntl:rs1_bypass_hold 
 rs1_bypass_mux_out : ex : output
Connects down to:ex_ctl:ex_ctl:rs1_bypass_mux_out , ex_ctl:ex_ctl:zero_addr_e , ex_dpath:ex_dpath:rs1_bypass_mux_out , imdr:ex_imdr:ie_dataB_d 
Connects up to:iu:ex:iu_rs1_e 
 rs1_bypass_mux_out : ex_ctl : input
Connects down to:ff_sre_6:shift_count_e1_flop:din , mux3_6:shift_count_mux:in2 , mux3_6:shift_count_mux:in1 
Connects up to:ex:ex_ctl:rs1_bypass_mux_out 
 rs1_bypass_mux_out : ex_dpath : output
Connects down to:ff_s_32:rs1_bypass_reg:din , buf10_drv_32:buf_rs1:out , mux5_32:shifter_src1_mux:in1 , mux5_32:bit_mux:in4 , mux5_32:bit_mux:in2 , mux5_32:bit_mux:in1 , mux5_32:bit_mux:in0 , mux8_32:alu_out_mux:in0 
Connects up to:ex:ex_dpath:rs1_bypass_mux_out 
 rs1_bypass_mux_out_gen : ex_dpath : wire
Connects down to:mux5_32:rs1_bypass_mux:out , buf10_drv_32:buf_rs1:in , inv10_drv_32:inv_rs1_1:in 
 rs1_bypass_mux_out_inv : ex_dpath : wire
Connects down to:inv10_drv_32:inv_rs1_1:out , inv10_drv_32:inv_rs1_2:in , inv10_drv_32:inv_rs1_3:in 
 rs1_bypass_mux_out_v1 : ex_dpath : wire
Connects down to:inv10_drv_32:inv_rs1_2:out , mux4_32:ucode_alu_a_mux:in3 , mux4_32:ucode_alu_a_mux:in2 , mux4_32:ucode_alu_a_mux:in0 , mux8_32:ucode_alu_b_mux:in6 , mux8_32:ucode_alu_b_mux:in3 , mux2_32:ucode_porta_mux:in0 
 rs1_bypass_mux_out_v2 : ex_dpath : wire
Connects down to:inv10_drv_32:inv_rs1_3:out , mux3_32:cmp_porta_mux:in0 , mux3_32:cmp_src1_mux:in2 , mux3_32:cmp_src2_mux:in1 , mux3_32:cmp_src2_mux:in0 , mux8_32:adder2_src1_mux:in6 , mux8_32:adder2_src1_mux:in5 
 rs1_bypass_mux_sel : ex : input
Connects down to:ex_dpath:ex_dpath:rs1_bypass_mux_sel 
Connects up to:iu:ex:rs1_forward_mux_sel , iu:ex:rs1_bypass_hold 
 rs1_bypass_mux_sel : ex_dpath : input
Connects down to:ff_sre_4:flop_rs1_bypass_sel:din , ff_sr:flop_rs1_bypass_sel_4:din 
Connects up to:ex:ex_dpath:rs1_bypass_mux_sel 
 rs1_bypass_mux_sel_e : ex_dpath : wire
Connects down to:ff_sre_4:flop_rs1_bypass_sel:out , ff_sr:flop_rs1_bypass_sel_4:out , mux5_32:rs1_bypass_mux:sel , mux5:rs1_0_bypass_mux:sel 
 rs1_bypass_vld : pipe : input
Connects down to:pipe_cntl:pipe_cntl:rs1_bypass_vld 
Connects up to:iu:pipe:iu_bypass_rs1_e 
 rs1_bypass_vld : pipe_cntl : input
Connects up to:pipe:pipe_cntl:rs1_bypass_vld 
 rs1_data : rcu_dpath : wire
Connects down to:mux2_32:mux_final_data_rs1:out , ff_s_32:flop_rs1_data:din 
 rs1_data_e : iu : wire
Connects down to:ex:ex:ru_rs1_e , rcu:rcu:rs1_data_e 
 rs1_data_e : rcu : output
Connects down to:rcu_dpath:rcu_dpath:rs1_data_e 
Connects up to:iu:rcu:rs1_data_e 
 rs1_data_e : rcu_dpath : output
Connects down to:ff_s_32:flop_rs1_data:out 
Connects up to:rcu:rcu_dpath:rs1_data_e 
 rs1_forward_mux_sel : iu : wire
Connects down to:ex:ex:rs1_bypass_mux_sel , rcu:rcu:rs1_forward_mux_sel , pipe:pipe:ru_byp_rs1_e_hit 
 rs1_forward_mux_sel : rcu : output
Connects down to:rcu_ctl:rcu_ctl:rs1_forward_mux_sel 
Connects up to:iu:rcu:rs1_forward_mux_sel 
 rs1_forward_mux_sel : rcu_ctl : output
Connects up to:rcu:rcu_ctl:rs1_forward_mux_sel 
 rs1_l : ucode : wire
Connects down to:inv_a_32:inv_a_32_0:out_l , inv_c_32:inv_c_32_0:inp 
 rs1_mux_out : ex_dpath : wire
Connects down to:mux2_32:rs1_mux:out , mux5_32:rs1_bypass_mux:in0 
 rs1_mux_sel : ex_dpath : wire
Connects down to:mux2_32:rs1_mux:sel , ff_sr:flop_rs1_mux:out , mux2:rs1_0_mux:sel 
 rs1_mux_sel_din : ex : input
Connects down to:ex_dpath:ex_dpath:rs1_mux_sel_din 
Connects up to:iu:ex:rs1_mux_sel_din 
 rs1_mux_sel_din : ex_dpath : input
Connects down to:ff_sr:flop_rs1_mux:din 
Connects up to:ex:ex_dpath:rs1_mux_sel_din 
 rs1_mux_sel_din : iu : wire
Connects down to:ex:ex:rs1_mux_sel_din , pipe:pipe:rs1_mux_sel_din 
 rs1_mux_sel_din : pipe : output
Connects down to:pipe_cntl:pipe_cntl:rs1_mux_sel_din 
Connects up to:iu:pipe:rs1_mux_sel_din 
 rs1_mux_sel_din : pipe_cntl : output
Connects up to:pipe:pipe_cntl:rs1_mux_sel_din 
 rs2 : ucode : input
Connects down to:ucode_dpath:ucode_dpath_0:rs2 
Connects up to:iu:ucode:iu_rs2_e 
 rs2 : ucode_dat : input
Connects down to:mj_s_mux6_d_32:mux6_w_mx_a:in3 , mj_s_mux4_d_32:mux4_w_mx_b0:in3 , mj_s_mux8_d_32:mux8_a_oprd:in6 
Connects up to:ucode_dpath:ucode_dat_0:rs2 
 rs2 : ucode_dpath : input
Connects down to:ucode_dat:ucode_dat_0:rs2 
Connects up to:ucode:ucode_dpath_0:rs2_0 , ucode:ucode_dpath_0:rs2 
 rs2zero : branch_dec : input
Connects down to:mj_s_mux4_d:m0:in2 
Connects up to:code_seq_cntl:branchd:rs2zero 
 rs2zero : code_seq : input
Connects down to:code_seq_cntl:p_code_seq_cntl:rs2zero 
Connects up to:fpu:cs:rs2zero 
 rs2zero : code_seq_cntl : input
Connects down to:branch_dec:branchd:rs2zero 
Connects up to:code_seq:p_code_seq_cntl:rs2zero 
 rs2zero : fpu : wire
Connects down to:rsadd:rsa:rs2zero , code_seq:cs:rs2zero 
 rs2zero : rsadd : output
Connects down to:rsadd_cntl:p_rsadd_cntl:rs2zero 
Connects up to:fpu:rsa:rs2zero 
 rs2zero : rsadd_cntl : output
Connects up to:rsadd:p_rsadd_cntl:rs2zero 
 rs2_0 : ex_dpath : wire
Connects down to:mux5:rs2_0_bypass_mux:out 
 rs2_0 : ucode : wire
Connects down to:inv_b_1:inv_b_1_1:out_l , ucode_dpath:ucode_dpath_0:rs2 
 rs2_0_l : branch_bit : input
Connects up to:ucode_add:branch_bit_0:rs2_0_l 
 rs2_0_l : ucode : input
Connects down to:inv_b_1:inv_b_1_1:inp , ucode_ctrl:ucode_ctrl_0:rs2_0_l 
Connects up to:iu:ucode:iu_rs2_e_0_l 
 rs2_0_l : ucode_add : input
Connects down to:branch_bit:branch_bit_0:rs2_0_l 
Connects up to:ucode_ctrl:ucode_add_0:rs2_0_l 
 rs2_0_l : ucode_ctrl : input
Connects down to:ucode_add:ucode_add_0:rs2_0_l 
Connects up to:ucode:ucode_ctrl_0:rs2_0_l 
 rs2_bypass_hold : ex_dpath : wire
Connects down to:ff_s_32:rs2_bypass_reg:out , mux5_32:rs2_bypass_mux:in4 , mux5:rs2_0_bypass_mux:in4 
 rs2_bypass_hold : iu : wire
Connects down to:ex:ex:rs2_bypass_mux_sel , pipe:pipe:rs2_bypass_hold 
 rs2_bypass_hold : pipe : output
Connects down to:pipe_cntl:pipe_cntl:rs2_bypass_hold 
Connects up to:iu:pipe:rs2_bypass_hold 
 rs2_bypass_hold : pipe_cntl : output
Connects up to:pipe:pipe_cntl:rs2_bypass_hold 
 rs2_bypass_mux_out : ex : output
Connects down to:ex_dpath:ex_dpath:rs2_bypass_mux_out , imdr:ex_imdr:ie_dataA_d 
Connects up to:iu:ex:iu_rs2_e 
 rs2_bypass_mux_out : ex_dpath : output
Connects down to:ff_s_32:rs2_bypass_reg:din , buf10_drv_32:buf_rs2_1:out , ff_se_32:rs2_bypass_mux_out_reg:din , mux5_32:shifter_src1_mux:in3 , mux5_32:shifter_src1_mux:in2 , mux3_32:shifter_src2_mux:in1 
Connects up to:ex:ex_dpath:rs2_bypass_mux_out 
 rs2_bypass_mux_out_d1 : ex_dpath : wire
Connects down to:ff_se_32:rs2_bypass_mux_out_reg:out , mux5_32:shifter_src1_mux:in4 , mux3_32:shifter_src2_mux:in2 
 rs2_bypass_mux_out_gen : ex_dpath : wire
Connects down to:mux5_32:rs2_bypass_mux:out , buf10_drv_32:buf_rs2_1:in , buf10_drv_32:buf_rs2_2:in 
 rs2_bypass_mux_out_v1 : ex_dpath : wire
Connects down to:buf10_drv_32:buf_rs2_2:out , mux8_32:ucode_alu_b_mux:in0 , mux3_32:cmp_porta_mux:in2 , mux3_32:cmp_src1_mux:in1 , mux3_32:cmp_src1_mux:in0 , mux8_32:adder2_src1_mux:in4 , mux2_32:iu_data_mux:in0 
 rs2_bypass_mux_sel : ex : input
Connects down to:ex_dpath:ex_dpath:rs2_bypass_mux_sel 
Connects up to:iu:ex:rs2_forward_mux_sel , iu:ex:rs2_bypass_hold 
 rs2_bypass_mux_sel : ex_dpath : input
Connects down to:ff_sre_4:flop_rs2_bypass_sel:din , ff_sr:flop_rs2_bypass_sel_4:din 
Connects up to:ex:ex_dpath:rs2_bypass_mux_sel 
 rs2_bypass_mux_sel_e : ex_dpath : wire
Connects down to:ff_sre_4:flop_rs2_bypass_sel:out , ff_sr:flop_rs2_bypass_sel_4:out , mux5_32:rs2_bypass_mux:sel , mux5:rs2_0_bypass_mux:sel 
 rs2_bypass_vld : pipe : input
Connects down to:pipe_cntl:pipe_cntl:rs2_bypass_vld 
Connects up to:iu:pipe:iu_bypass_rs2_e 
 rs2_bypass_vld : pipe_cntl : input
Connects up to:pipe:pipe_cntl:rs2_bypass_vld 
 rs2_data : rcu_dpath : wire
Connects down to:mux2_32:mux_final_data_rs2:out , ff_s_32:flop_rs2_data:din 
 rs2_data_e : iu : wire
Connects down to:ex:ex:ru_rs2_e , rcu:rcu:rs2_data_e 
 rs2_data_e : rcu : output
Connects down to:rcu_dpath:rcu_dpath:rs2_data_e 
Connects up to:iu:rcu:rs2_data_e 
 rs2_data_e : rcu_dpath : output
Connects down to:ff_s_32:flop_rs2_data:out 
Connects up to:rcu:rcu_dpath:rs2_data_e 
 rs2_forward_mux_sel : iu : wire
Connects down to:ex:ex:rs2_bypass_mux_sel , rcu:rcu:rs2_forward_mux_sel , pipe:pipe:ru_byp_rs2_e_hit 
 rs2_forward_mux_sel : rcu : output
Connects down to:rcu_ctl:rcu_ctl:rs2_forward_mux_sel 
Connects up to:iu:rcu:rs2_forward_mux_sel 
 rs2_forward_mux_sel : rcu_ctl : output
Connects up to:rcu:rcu_ctl:rs2_forward_mux_sel 
 rs2_inst_1 : ifu : wire
Connects down to:mux2_8:mux_opcode_1_rs1:in1 , mux4_24:mux_rs2_inst:out , mux2_8:mux_opcode_1_rs2:in0 
 rs2_inst_2 : ifu : wire
Connects down to:mux2_8:mux_opcode_2_rs1_swap:in1 , mux4_24:mux_rs2_inst:out , mux2_8:mux_opcode_2_rs2_swap:in0 , mux5_8:mux_offset_rs2:in4 
 rs2_inst_3 : ifu : wire
Connects down to:mux2_8:mux_offset_2_rs2_swap:in1 , mux4_24:mux_rs2_inst:out , mux2_8:mux_opcode_2_rs2:in0 
 rs32 : branch_dec : input
Connects down to:branch_decode1:b1:rs32 , branch_decode2:b2:rs32 , branch_decode3:b3:rs32 , branch_decode4:b4:rs32 
Connects up to:code_seq_cntl:branchd:rs32 
 rs32 : branch_decode1 : input
Connects up to:branch_dec:b1:rs32 
 rs32 : branch_decode2 : input
Connects up to:branch_dec:b2:rs32 
 rs32 : branch_decode3 : input
Connects up to:branch_dec:b3:rs32 
 rs32 : branch_decode4 : input
Connects up to:branch_dec:b4:rs32 
 rs32 : code_seq : input
Connects down to:code_seq_cntl:p_code_seq_cntl:rs32 
Connects up to:fpu:cs:rs32 
 rs32 : code_seq_cntl : input
Connects down to:branch_dec:branchd:rs32 
Connects up to:code_seq:p_code_seq_cntl:rs32 
 rs32 : exponent : output wire
Connects down to:exponent_cntl:p_exponent_cntl:rs32 
Connects up to:fpu:exp:rs32 
 rs32 : exponent_cntl : output
Connects up to:exponent:p_exponent_cntl:rs32 
 rs32 : fpu : wire
Connects down to:exponent:exp:rs32 , rsadd:rsa:rs32 , code_seq:cs:rs32 
 rs32 : rsadd : input
Connects down to:rsadd_cntl:p_rsadd_cntl:rs32 
Connects up to:fpu:rsa:rs32 
 rs32 : rsadd_cntl : input
Connects down to:rsadd_dec:rsadec:rs32 
Connects up to:rsadd:p_rsadd_cntl:rs32 
 rs32 : rsadd_dec : input
Connects up to:rsadd_cntl:rsadec:rs32 
 rsa : rsft31_63i_32o : input
Connects up to:rshifter:fpu_dp_cells_rshift:saout 
 rsfunc : fpu : wire
Connects down to:rsadd:rsa:rsfunc , code_seq:cs:mword 
 rsfunc : rsadd : input
Connects down to:rsadd_cntl:p_rsadd_cntl:rsfunc 
Connects up to:fpu:rsa:rsfunc 
 rsfunc : rsadd_cntl : input
Connects down to:rsadd_dec:rsadec:rsfunc 
Connects up to:rsadd:p_rsadd_cntl:rsfunc 
 rsfunc : rsadd_dec : input
Connects up to:rsadd_cntl:rsadec:rsfunc 
 rsf_out : rsft31_63i_32o : output
Connects up to:rshifter:fpu_dp_cells_rshift:rshiftout 
 rsge64 : branch_dec : input
Connects down to:branch_decode1:b1:rsge64 , branch_decode2:b2:rsge64 , branch_decode3:b3:rsge64 , branch_decode4:b4:rsge64 
Connects up to:code_seq_cntl:branchd:rsge64 
 rsge64 : branch_decode1 : input
Connects up to:branch_dec:b1:rsge64 
 rsge64 : branch_decode2 : input
Connects up to:branch_dec:b2:rsge64 
 rsge64 : branch_decode3 : input
Connects up to:branch_dec:b3:rsge64 
 rsge64 : branch_decode4 : input
Connects up to:branch_dec:b4:rsge64 
 rsge64 : code_seq : input
Connects down to:code_seq_cntl:p_code_seq_cntl:rsge64 
Connects up to:fpu:cs:rsge64 
 rsge64 : code_seq_cntl : input
Connects down to:branch_dec:branchd:rsge64 
Connects up to:code_seq:p_code_seq_cntl:rsge64 
 rsge64 : exponent : output wire
Connects down to:exponent_cntl:p_exponent_cntl:rsge64 
Connects up to:fpu:exp:rsge64 
 rsge64 : exponent_cntl : output
Connects up to:exponent:p_exponent_cntl:rsge64 
 rsge64 : fpu : wire
Connects down to:exponent:exp:rsge64 , code_seq:cs:rsge64 
 rsh : rsh16_33 : input
Connects down to:mx16_1:mx16_1_32:sel , mx16_2:mx16_2_30:sel , mx16_2:mx16_2_28:sel , mx16_2:mx16_2_26:sel , mx16_2:mx16_2_24:sel , mx16_2:mx16_2_22:sel , mx16_2:mx16_2_20:sel , mx16_2:mx16_2_18:sel , mx16_2:mx16_2_16:sel , mx16_2:mx16_2_14:sel , mx16_2:mx16_2_12:sel , mx16_2:mx16_2_10:sel , mx16_2:mx16_2_08:sel , mx16_2:mx16_2_06:sel , mx16_2:mx16_2_04:sel , mx16_2:mx16_2_02:sel , mx16_2:mx16_2_00:sel 
Connects up to:imdr_dpath:rsh16_33_b:sel_rsh_b 
 rshiftout : rsadd_dp : wire
Connects down to:rshifter:rshift1:rshiftout , cla_adder_32:rsadder:in2 
 rshiftout : rshifter : output
Connects down to:rsft31_63i_32o:fpu_dp_cells_rshift:rsf_out 
Connects up to:rsadd_dp:rshift1:rshiftout 
 rsneg : branch_dec : input
Connects down to:mj_s_mux4_d:m0:in0 
Connects up to:code_seq_cntl:branchd:rsneg 
 rsneg : code_seq : input
Connects down to:code_seq_cntl:p_code_seq_cntl:rsneg 
Connects up to:fpu:cs:rsneg 
 rsneg : code_seq_cntl : input
Connects down to:branch_dec:branchd:rsneg 
Connects up to:code_seq:p_code_seq_cntl:rsneg 
 rsneg : fpu : wire
Connects down to:rsadd:rsa:rsneg , code_seq:cs:rsneg 
 rsneg : rsadd : output
Connects down to:rsadd_cntl:p_rsadd_cntl:rsneg 
Connects up to:fpu:rsa:rsneg 
 rsneg : rsadd_cntl : output
Connects up to:rsadd:p_rsadd_cntl:rsneg 
 rsout : fpu : wire
Connects down to:rsadd:rsa:rsout , mantissa:man:rsout 
 rsout : mantissa : input
Connects down to:mantissa_dp:i_mantissa_dp:rsout 
Connects up to:fpu:man:rsout 
 rsout : mantissa_dp : input
Connects down to:mj_s_mux8_d_32:na1:in1 , mj_s_mux6_d_32:na0:in0 
Connects up to:mantissa:i_mantissa_dp:rsout 
 rsout : rsadd : output
Connects down to:rsadd_dp:p_rsadd_dp:rsout , rsadd_cntl:p_rsadd_cntl:rsout_11_0 , rsadd_cntl:p_rsadd_cntl:rsout_31_30 
Connects up to:fpu:rsa:rsout 
 rsout : rsadd_dp : output
Connects down to:cla_adder_32:rsadder:sum 
Connects up to:rsadd:p_rsadd_dp:rsout 
 rsout_11_0 : rsadd_cntl : input
Connects down to:round_dec:rs2:in 
Connects up to:rsadd:p_rsadd_cntl:rsout 
 rsout_31_30 : rsadd_cntl : input
Connects up to:rsadd:p_rsadd_cntl:rsout 
 rsovf : exponent : input
Connects down to:exponent_dp:p_exponent_dp:rsovf 
Connects up to:fpu:exp:rsovf 
 rsovf : exponent_dp : input
Connects up to:exponent:p_exponent_dp:rsovf 
 rsovf : fpu : wire
Connects down to:exponent:exp:rsovf , incmod:inc:rsovf , rsadd:rsa:rsovf 
 rsovf : incmod : input
Connects up to:fpu:inc:rsovf 
 rsovf : rsadd : output
Connects down to:rsadd_cntl:p_rsadd_cntl:out 
Connects up to:fpu:rsa:rsovf 
 rsovfi : branch_dec : input
Connects down to:mj_s_mux4_d:m0:in1 
Connects up to:code_seq_cntl:branchd:rsovfi 
 rsovfi : code_seq : input
Connects down to:code_seq_cntl:p_code_seq_cntl:rsovfi 
Connects up to:fpu:cs:rsovfi 
 rsovfi : code_seq_cntl : input
Connects down to:branch_dec:branchd:rsovfi 
Connects up to:code_seq:p_code_seq_cntl:rsovfi 
 rsovfi : fpu : wire
Connects down to:rsadd:rsa:rsovfi , code_seq:cs:rsovfi 
 rsovfi : rsadd : output
Connects down to:rsadd_dp:p_rsadd_dp:rsovfi , rsadd_cntl:p_rsadd_cntl:rsovfi 
Connects up to:fpu:rsa:rsovfi 
 rsovfi : rsadd_cntl : input
Connects down to:mj_s_ff_snre_d_3:ff:din 
Connects up to:rsadd:p_rsadd_cntl:rsovfi 
 rsovfi : rsadd_dp : output
Connects down to:cla_adder_32:rsadder:cout 
Connects up to:rsadd:p_rsadd_dp:rsovfi 
 rsround : incin_dec : input
Connects up to:rsadd_cntl:id0:rsround 
 rsround : rsadd_cntl : wire
Connects down to:round_dec:rs2:roundout , incin_dec:id0:rsround 
 rule_15_cp : ucode_monitor : reg
 rule_15_frame : ucode_monitor : reg
 rule_15_vars : ucode_monitor : reg
 rule_16_optop : ucode_monitor : reg
 rule_16_optop_changed : ucode_monitor : integer
 rule_16_optop_change_requested : ucode_monitor : wire
 rule_16_optop_latched : ucode_monitor : integer
 rule_17_invoke_in_e : ucode_monitor : wire
 rule_2_s_cache_addr : ucode_monitor : reg
 rule_9_optop : ucode_monitor : reg
 rule_9_vars : ucode_monitor : reg
 ru_byp_rs1_e_hit : pipe : input
Connects down to:pipe_cntl:pipe_cntl:ru_byp_rs1_e_hit 
Connects up to:iu:pipe:rs1_forward_mux_sel 
 ru_byp_rs1_e_hit : pipe_cntl : input
Connects down to:ff_sre:flop_bypass_rs1_hit:din 
Connects up to:pipe:pipe_cntl:ru_byp_rs1_e_hit 
 ru_byp_rs1_e_hit_e : pipe_cntl : wire
Connects down to:ff_sre:flop_bypass_rs1_hit:out 
 ru_byp_rs2_e_hit : pipe : input
Connects down to:pipe_cntl:pipe_cntl:ru_byp_rs2_e_hit 
Connects up to:iu:pipe:rs2_forward_mux_sel 
 ru_byp_rs2_e_hit : pipe_cntl : input
Connects down to:ff_sre:flop_bypass_rs2_hit:din 
Connects up to:pipe:pipe_cntl:ru_byp_rs2_e_hit 
 ru_byp_rs2_e_hit_e : pipe_cntl : wire
Connects down to:ff_sre:flop_bypass_rs2_hit:out 
 ru_rs1_e : ex : input
Connects down to:ex_dpath:ex_dpath:ru_rs1_e 
Connects up to:iu:ex:rs1_data_e 
 ru_rs1_e : ex_dpath : input
Connects down to:mux2_32:rs1_mux:in0 , mux2:rs1_0_mux:in0 
Connects up to:ex:ex_dpath:ru_rs1_e 
 ru_rs2_e : ex : input
Connects down to:ex_dpath:ex_dpath:ru_rs2_e 
Connects up to:iu:ex:rs2_data_e 
 ru_rs2_e : ex_dpath : input
Connects down to:mux5_32:rs2_bypass_mux:in0 , mux5:rs2_0_bypass_mux:in0 
Connects up to:ex:ex_dpath:ru_rs2_e 
 r_addr : ucode_seq : wire
Connects down to:inc9:inc9_rom_add1:ai , inc8:inc8_rom_add2:ai , fa9:fa9_rom_add3:a 
 r_extreme : imdr_ctrl : wire
 r_extreme_r : imdr_ctrl : wire
Connects down to:ff_sr_3:ff_sr_3_2:out 
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This page: Created:Wed Mar 24 09:42:58 1999
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