PPT 슬라이드
Gate Array Conversion HardWire
Functional ? Simulation vectors must ? No simulation vectors Compatibility be developed
? Redesign required ? 100% Pin & Functional ? Some gates and nets are lost ? CLBs and Nets preserved
Timing ? Post route timing simulation ? Simple timing analysis
Compatibility always required without simulation
? Non-exhaustive ? Asynchronous path focus
Testability ? Fault Coverage varies 70 - 95% ? ᢗ% Fault Coverage
? Test Vectors development and ? Test vectors created
Fault Grading required automatically
Result ? Resource intensive ? Easy, virtually no work
? Medium to high risk ? Lowest risk