Recently Published Application Notes

• Implementing an 8b/10b Encoder/Decoder for Gigabit Ethernet in the Actel SX FPGA Family
  This application note describes how an Actel A54SX16 FPGA was used to implement an 8b/10b encoder/decoder function for a Gigabit Ethernet router.

• Minimizing Single Event Upset Effects Using Synplicity
  The resistance of an Actel device to single event upset (SEU) effects can be influenced by using certain logic design techniques. This application note gives an overview of some SEU resistant design techniques and describes how to implement these techniques using Synplicity.

• RTL Register-Based Memory Implementations
  This application note describes how to build and test a high speed register SRAM or FIFO given RTL code. With a small memory requirement, you can synthesize to a non-SRAM-based Actel family, such as the XL or ACT 3 families. Download ASCII file with code only.

• Minimizing Single Event Upset Effects Using Synopsys
  The resistance of an Actel device to single event upset (SEU) effects can be influenced by using certain logic design techniques. This application note gives an overview of some SEU resistant design techniques and describes how to implement these techniques using Synopsys.

• Design Techniques for Radiation-Hardened FPGAs
  Actel Corporation introduces radiation-hardened versions of the popular A1280 and A1020 field programmable gate array (FPGA) familes. These products are processed to the QML process flow as defined in MIL-PRF-38535. They are manufactured with a 0.8 micron, two-level metal epitaxial bulk CMOS technology, and offer total dose radiation-hardness in excess of 300K rads (Si) with guaranteed latch-up immunity. Because of this high total dose capability, the RH1280 and RH1020 are intended for use in applications including Earth orbiting satellites, deep space probes, and military electronics.

• Commercial to Radiation-Hardened Design Migration
  Because the environmental properties of radiation-hardened devices are not required for design prototyping, Actel provides less expensive, compatible commercial devices for this purpose. Although the radiation-hardened devices and the commercial versions are functional equivalents and footprint compatible, they differ in their timing characteristics because of differences in their process geometries. This application note describes design practices that make it easy to verify timing when using commercial devices as prototypes for radiation-hardened devices. Many of these suggested design practices can also improve design completion time.

• Designing FIR Filters with Actel FPGAs
  In this application note, two architectures for FIR (finite impulse response) filters are described. The FIR filter is the most common DSP application, and the techniques illustrated in this application note should pertain to other DSP applications as well.

• Verifying Setup and Hold Times in Timing Tools
  Used together, static timing analysis and simulation complement each other to provide complete design verification. This application note explains how to create a setup and hold timing report and how to address any timing issues that may arise.

• Power-Up Design Considerations
  The state of a system at startup is an important consideration in designing a circuit. It is usually desirable to provide an input signal at startup to reset synchronous circuitry. Otherwise, the system may initially operate in an unpredictable fashion because flip-flops are not designed to power-on in any particular state. This application note describes the power-on conditions of an Actel device and a recommended POR circuit.

• Designing Telecommunication Applications Using Digital Signal Processing Functions with FPGAs
  This application note illustrates the use of a digital signal processing (DSP) core targeted to Actel's A32200DX field programmable gate array. Performance and utilization results are reported, along with the design flow. Techniques discussed in this note can be applied to other similar applications.

• High-Level Design Benchmark Report
  This report shows examples of complex designs where engineers used Actel's FPGAs with synthesis flows to solve their tough design problems.

• Optimal Datapath Generation Using ACTgen
  Actel's ACTgen is the central resource for building datapath logic functions. ACTgen is built on a datapath synthesis engine with hand-optimized algorithms that have been designed to maximize performance and to minimize logic costs.

• Timing Analysis: The Key to High Performance System Logic Design
  Achieving needed timing requires both skill and experience. Actel provides fast, accurate, and reliable timing analysis tools to ease the design process and meet timing requirements.

• Using Silicon Explorer to Debug the 100 Mbit Ethernet Dual-Port Bridge
  This note describes a working 100Mbit/10Mbit Ethernet bridge using Actel A1280XL FPGAs. Several techniques were used during the design, test, and debugging of the design, which could be applied to a variety of design problems.