 ACEX
Device Families 
The
ACEX Initiative
Altera's new ACEX initiative provides industry-leading
price points for low-cost, high-performance design needs.
The ACEX strategy will offer mid-range density,
look-up-table-based programmable logic devices (PLDs)
offering the low cost and high performance needed for
price-sensitive communications applications. Combining
industry-leading price points with feature-rich architectures,
ACEX devices can effectively fulfill the needs of communications
applications via system speeds of up to 200 MHz and
price points as low as $3.50.
The ACEX initiative consists of a
series of PLD families. The first of these, the
ACEX 1K device family, will operate at 2.5-V while the
second, the ACEX 2K device family, will operate at 1.8-V.
Further ACEX device families will follow as new
process technologies and PLD advancements allow for
a continuing roadmap towards ever lower price points.
Ideal for Cost-Sensitive Applications
The ACEX family addresses applications
in the communications marketplace that need the flexibility
and ease-of-use of PLDs, as well as low cost for volume
production. This need for high-performance, low-cost
PLDs is especially crucial for communications applications
such as xDSL modems, cable modems, remote access concentrators,
access routers, and low-cost switches. In the
communications market, flexibility and time-to-market
advantages are crucial but high-volume systems require
a truly cost-effective solution. ACEX devices
meet this need with high performance and volume pricing
as low as $3.50.
Industry-Leading Process Technology
ACEX devices are manufactured using
the industry's most efficient process technologies and
most advanced capabilities. ACEX 1K devices make
use of an advanced 2.5-V, 0.22-micron/0.18-micron 5-layer-metal
hybrid synchronous random access memory (SRAM) process.
This process provides the advantages of a 2.5-V
core and full 5-V I/O tolerance through the use of 0.22-micron
transistors while generating significant die size advantages
via the use of a 0.18-micron metal interconnect.
The ACEX 2K family will make use of an industry-leading
0.18-micron 6-layer metal SRAM process.
In addition, both ACEX 1K and ACEX
2K devices make use of the patented Altera redundancy
technology in order to provide significant yield improvements
and to further drive down device costs. The net
result is fully optimized process technologies that
can support the lowest price per function in the PLD
industry.
The
ACEX 1K Device Family
ACEX 1K devices range from 10,000 to 100,000 typical
gates (56,000 to 257,000 maximum system gates) and provide
high performance and features that enable the effective
implementation of low-cost, high-performance communications
solutions.
All ACEX 1K devices feature high-performance
embedded RAM blocks that can implement dual-port RAM,
(read-only memory) ROM, (first-in first-out buffers)
FIFOs or logic. Full 64-bit/66MHz (peripheral
component interconnect) PCI support is provided in order
to fulfill a key requirement in many high-performance
communications systems. ACEX devices also feature
(phase locked loop) PLL support for clock management,
including the ClockLock feature to improve I/O performance
and the ClockBoost feature to multiply the system clock
inside the ACEX 1K device. ACEX 1K devices also
feature MultiVolt I/O operation, enabling them to interface
with devices running at 5.0-V, 3.3-V, and 2.5-V. ACEX
1K devices make use of low-cost packaging technologies,
including advanced FineLine BGA packages featuring SameFrame migration capability.
Table 1 summarizes
the ACEX 1K family:
Table 1: ACEX Device Family |
Device |
EP1K10 |
EP1K30 |
EP1K50 |
EP1K100 |
Typical gates |
10,000 |
30,000 |
50,000 |
100,000 |
Maximum system gates |
56,000 |
119,000 |
199,000 |
257,000 |
Logic Elements (LEs) |
576 |
1,728 |
2,880 |
4,992 |
Embedded Array Blocks
(EABs) |
3 |
6 |
10 |
12 |
Total RAM Bits |
12,288 |
24,576 |
40,960 |
49,152 |
User I/O Pins |
130 |
171 |
249 |
333 |
The
ACEX 2K Device Family
The ACEX 2K family is based on an industry-leading
1.8-V, 0.18-micron, 6-layer metal SRAM process, and
will feature devices ranging in density from 20,000
to 150,000 gates. The devices provide several key features,
including embedded dual-port RAM blocks, emerging I/O
standard support, PCI-X compatibility, 64-bit, 66-MHz
PCI compatibility, phase locked loop support, and advanced
packaging in Fineline BGA and quad flat pack (QFP) packages.
Software Support & Availability
ACEX 1K devices will be available
this month and associated software support will be available
in the MAX+PLUS II ® software version 9.6. Version 9.5
and 9.6 of the MAX+PLUS II software include advanced
algorithms that increase design performance by 30% and
allow for 30x faster compile times than previous versions
of MAX+PLUS II software. These algorithmic improvements
have been applied to the ACEX 1K device family and will
enable fast and effective design for ACEX 1K devices.
ACEX 2K devices will be supported
in a future version of the Quartus development tool which includes the following
state-of-the-art features:
- Block-level editing
- Integration with standard source-control
software
- Expanded support for megafunctions
- Consistent performance enhancements
to achieve the silicon's full potential
- Internet integration
- Fast compilation times
Intellectual
Property
ACEX
devices can implement a wide variety of intellectual
property (IP) functions, making it easy to create fast,
effective designs. Check out the IP MegaStore on this web site for more information on
Altera MegaCore and Altera MegaFunction
Partners Program (AMPPSM) IP functions.
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High-end, High-density, High-performance가 Target인
저가형 Device입니다... XILINX의
Spartan II에 대항하는 제품인 것 같네요... (2000.7.4)
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