E+MAX¿Í MAX+PLUS II BASELINE ¼ÒÇÁÆ®¿þ¾î
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¾ËÅ×¶ó´Â ÇÁ·Î±×·¡¸Óºí ·ÎÁ÷ µð¹ÙÀ̽ºÀÇ ´Ù¾çÇÑ ÁýÀûµµ¸¦ µÎ·ç ¼³°èÇÒ ¼ö ÀÖ´Â E+MAX¿Í MAX+PLUS II BASELINE ¼ÒÇÁÆ®¿þ¾î¶ó°í
ÇÏ´Â ¹«·á ¼ÒÇÁÆ®¿þ¾î ÆÐŰÁö¸¦ Á¦°øÇϰí ÀÖ´Ù.
»õ ±â´É
E+MAX ¼ÒÇÁÆ®¿þ¾î´Â product-term ÇÁ·Î±×·¡¸Óºí ·ÎÁ÷ µð¹ÙÀ̽º(PLD)¸¦ ¼³°èÇϰí ÇÁ·Î±×·¥ÇÒ ¼ö ÀÖ´Â ¼ÒÇÁÆ®¿þ¾î ÆÐŰÁöÀÌ´Ù.:
¾ËÅ×¶óÀÇ MAX®7000, 7000S, 7000A, 7000AE, 7000B ±×¸®°í
MAX 3000A µð¹ÙÀ̽º.
E+MAX ¼ÒÇÁÆ®¿þ¾î´Â ¾ËÅ×¶óÀÇ VHDL ¹× Verilog HDL synthesis,
schematic µðÀÚÀÎ ¿£Æ®¸®, ¸ðµç ±â´ÉÀÇ Å¸ÀÌ¹Ö ºÐ¼® ±×¸®°í ½Ã¹Ä·¹ÀÌ¼Ç ±â´ÉµéÀ» Æ÷ÇÔÇϰí ÀÖ´Ù.
E+MAX ¼ÒÇÁÆ®¿þ¾îÀÇ ÇöÀç ¹öÀüÀº 9.5 À̸ç ÃßÈÄ ¾÷±×·¹ÀÌµå µÉ »õ ¹öÀüÀº ¾ËÅ×¶óÀÇ VHDL ¹×
Verilog HDL synthesis¸¦ Æ÷ÇÔ ÇÏÁö ¾ÊÀ¸¸ç, ´ë½Å »ç¿ëÀÚ´Â ¸àÅä ±×·¡ÇȽº»çÀÇ LeonardoSpectrumÀ̳ª ½Ã³ô½Ã½º»çÀÇ
FPGA Express¸¦ ´Ù¿î·Îµå ¹ÞÀ» ¼ö ÀÖ°Ô µÈ´Ù. ÀÌ·¯ÇÑ ¼¼°èÀûÀÎ synthesis Åø°ú ´õºÒ¾î
E+MAX¼ÒÇÁÆ®¿þ¾î´Â ¾ËÅ×¶ó product-term PLD¿¡ ´ëÇÑ ¿ÏÀüÇÑ ¼Ö·ç¼ÇÀ» Á¦°øÇÑ´Ù.
MAX+PLUS II BASELINE ¼ÒÇÁÆ®¿þ¾î´Â Áß°£ ¹üÀ§ÀÇ ÁýÀûµµ¸¦ °¡Áø ·è¾÷ Å×À̺í PLD ¼³°è¿¡ ´ëÇÑ ¼ÒÇÁÆ®¿þ¾î ÆÐŰÁöÀÌ´Ù. ÀÌ
ÃÖ½ÅÀÇ ¹öÀü¿¡¼´Â ACEX 1K µð¹ÙÀ̽º Á¦Ç°±º¿¡ ´ëÇÑ ¼³°è ¹× ÄÁÇDZԷ¹ÀÌ¼Ç Áö¿øÀÌ Ãß°¡µÇ¾ú´Ù. MAX+PLUS II BASELINE
¼ÒÇÁÆ®¿þ¾î´Â AHDL synthesis, schematic µðÀÚÀÎ ¿£Æ®¸®, ¸ðµç ±â´ÉÀÇ Å¸ÀÌ¹Ö ºÐ¼® ±×¸®°í ½Ã¹Ä·¹ÀÌ¼Ç ±â´ÉÀ» Æ÷ÇÔÇϰí
ÀÖ´Ù.
2000³â 5¿ùºÎÅÍ »ç¿ëÀÚ´Â ¸àÅä ±×·¡ÇȽº»çÀÇ LeonardoSpectrumÀ̳ª ½Ã³ô½Ã½º»çÀÇ FPGA Express¸¦ ´Ù¿î·Îµå ¹Þ°í
¶óÀ̼¾½º ¹ÞÀ» ¼ö ÀÖ°Ô µÈ´Ù. ÀÌ·¯ÇÑ ¼¼°èÀûÀÎ synthesis Åø°ú ´õºÒ¾î MAX+PLUS II BASELINEÀº Áß°£ ¹üÀ§ÀÇ ÁýÀûµµ¸¦ °¡Áø
·è¾÷ Å×À̺í PLD¿¡ ´ëÇÑ ¿ÏÀüÇÑ ¼Ö·ç¼ÇÀ» Á¦°øÇÑ´Ù.
±â´É ºñ±³
E+MAX¿Í MAX+PLUS II BASELINE ¼ÒÇÁÆ®¿þ¾î´Â ¼³°è¸¦ ÀÔ·Â, ÄÄÆÄÀÏÇϰųª ŸÀÌ¹Ö ºÐ¼®À» ½ÇÇàÇÏ°í ´Ù¾çÇÑ ¾ËÅ×¶óÀÇ ÇÁ·Î±×·¡¸Óºí ·ÎÁ÷ µð¹ÙÀ̽º(PLD)¸¦ ÇÁ·Î±×·¥ÇÏ´Â µ¥ ÀÖ¾î¼ ²÷±è ¾ø´Â °³¹ß
Ç÷ο츦 Á¦°øÇÑ´Ù. E+MAX¿Í MAX+PLUS II BASELINE ¼ÒÇÁÆ®¿þ¾îÀÇ Áö¿ø °¡´ÉÇÑ µð¹ÙÀ̽º¿Í °¡´É ºñ±³¿¡ ´ëÇÏ¿© Ç¥1À» ÂüÁ¶ÇÒ ¼ö
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Ç¥ 1. E+MAX & MAX+PLUS II BASELINE ¼ÒÇÁÆ®¿þ¾î ±â´É |
¼ÒÇÁÆ®¿þ¾î ±â´Éºñ±³ |
E+MAX Version 9.5 |
MAX+PLUS II BASELINE Version 9.6
(1) |
µð¹ÙÀ̽º Áö¿ø |
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µðÀÚÀÎ ¿£Æ®¸® |
- Choice of Mentor Graphics LeonardoSpectrum or Synopsys FPGA Express
synthesis software for VHDL and Verilog support
- Text-based design entry using Altera nativeVHDL, Verilog,
or the Altera Hardware Description Language (AHDL)
- Schematic design entry
- Interfaces to popular EDA tools
- Floorplan editing
- Hierarchical design management
- Library of Parameterized Modules (LPM)
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- Choice of Mentor Graphics Leonardo Spectrum or Synopsys FPGA Express
synthesis software for VHDL and Verilog support
- Text-based design entry using the Altera Hardware Description Language
(AHDL)
- Schematic design entry
- Interfaces to popular EDA tools
- Floorplan editing
- Hierarchical design management
- Library of Parameterized Modules (LPM)
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µðÀÚÀÎ ÄÄÆÄÀÏ |
- Logic synthesis and automatic fitting
- Automatic error location in design files
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- Logic synthesis and automatic fitting
- Automatic error location in design files
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µðÀÚÀÎ °ËÁõ |
- Timing analysis
- Functional simulation
- Timing simulation
- Waveform analysis
- Creates output files for use with third-party simulators
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- Timing analysis
- Functional simulation
- Timing simulation
- Waveform analysis
- Creates output files for use with third-party simulators
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ÇÁ·Î±×·¡¹Ö |
µð¹ÙÀ̽º ÇÁ·Î±×·¡¹Ö (2)
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µð¹ÙÀ̽º ÇÁ·Î±×·¡¹Ö (2) |
´Ù¸¥ ±â´É |
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| Note:
- MAX+PLUS II BASELINE´Â EPF10K10, EPF10K10A, EPF10K20, EPF10K30, EPF10K30A, EPF10K30E, EPM9320, EPM9320A, EPF8452A, EPF8282A, ±×¸®°í Classic¢â µð¹ÙÀ̽º Á¦Ç°±º¿¡ ´ëÇÑ Áö¿øÀ» Æ÷ÇÔÇϰí ÀÖ´Ù.
- MAX+PLUS II ¼ÒÇÁÆ®¿þ¾î Ç® ¹öÀüÀÌ ¾ø¾îµµ MAX+PLUS II ÇÁ·Î±×·¡¸Ó ¾ÖÇø®ÄÉÀ̼ÇÀÇ stand-alone ¹öÀüÀÎ ¾ËÅ×¶óÀÇ
Stand-Alone Programmer (ASAP2) ¼ÒÇÁÆ®¿þ¾î¸¦ »ç¿ëÇÏ¿© ¾ËÅ×¶ó µð¹ÙÀ̽º¸¦ ÇÁ·Î±×·¥ÇÏ°í °ËÁõ ¹× Å×½ºÆ®ÇÒ ¼ö ÀÖ´Ù. ¿©±â¿¡¼ ASAP2¸¦ ´Ù¿î·Îµå ¹ÞÀ» ¼ö ÀÖ´Ù.
E+MAX¿Í MAX+PLUS II BASELINE ¼ÒÇÁÆ®¿þ¾î´Â stand-alone PC³ª TCI/IP ³×Æ®¿öÅ© ȯ°æ PCµéÀÇ À©µµ¿ì
95/98À̳ª À©µµ¿ì NT 4.0¿¡¼ ±¸µ¿µÈ´Ù. Ãß°¡ ½Ã½ºÅÛ »ç¾ç¿¡ °üÇÏ¿© MAX+PLUS II read.me ÆÄÀÏÀ» ÂüÁ¶ÇÒ ¼ö ÀÖ´Ù.
E+MAX 9.5 ¹öÀü
E-MAX ¼ÒÇÁÆ®¿þ¾î¸¦ »ç¿ëÇÏ·Á¸é E+MAX 9.5 ¹öÀüÀ» ´Ù¿î·Îµå ¹Þ¾Æ
¼³Ä¡ÇÏ¿©¾ß ÇÑ´Ù. ¶ÇÇÑ E+MAX ¶óÀ̼¾½º ÆÄÀÏÀ» ¿äûÇÏ¿© ¼³Ä¡ÇÏ¿©¾ß ÇÑ´Ù. ¶óÀ̼¾½º ÆÄÀÏÀ» ¿äûÇϱâ À§ÇÑ ¸µÅ©´Â ´Ù¿î·Îµå ÆäÀÌÁö¿¡¼ Á¦°øµÈ´Ù.
E+MAX ´Ù¿î·Îµå ÆÄÀÏÀº 33,645,037 ¹ÙÀÌÆ®ÀÌ´Ù. ´Ù¿î·Îµå ¹Þ´Âµ¥ °É¸®´Â ½Ã°£Àº »ç¿ëÇÏ´Â ÀÎÅÍ³Ý ¾×¼¼½ºÀÇ À¯Çü°ú ÀÎÅÍ³Ý ¸ÁÀÇ
È¥Àâµµ¿¡ ´Þ·ÁÀÖ´Ù. ¸¸¾à À¥ ºê¶ó¿ìÀú·Î ´Ù¿î·Îµå ¹Þ´Âµ¥ ¹®Á¦°¡ ÀÖÀ¸¸é FTP ÇÁ·Î±×·¥À» »ç¿ëÇÏ¿© ¾ËÅ×¶ó FTP »çÀÌÆ®ÀÎ ftp.altera.comÀÇ /pub/software µð·ºÅ丮³»¿¡
ÀÖ´Â ÆÄÀÏÀ» ´Ù¿î·Îµå ¹ÞÀ¸¸éµÈ´Ù. ¶ÇÇÑ
¸ðµç ¾ËÅ×¶ó ¹®Çå ¹× ÀÚ·á¿Í BASELINE 9.6 ¼ÒÇÁÆ®¿þ¾î¸¦ Æ÷ÇÔÇϰí ÀÖ´Â ¾ËÅ×¶óÀÇ µðÁöÅÐ ¶óÀ̺귯¸® CD-ROMÀ» ¿äÃ»ÇØµµ
(lit_req@altera.com¿¡ ¿äû) E+MAX ¼ÒÇÁÆ®¿þ¾î¸¦ ±¸ÇÒ ¼ö
ÀÖ´Ù.
E+MAX 9.5 ¹öÀü
´Ù¿î·Îµå ¹Þ±â
MAX+PLUS II BASELINE 9.6 ¹öÀü
MAX+PLUS II BASELINEÀ» »ç¿ëÇÏ·Á¸é MAX+PLUS II
BASELINE 9.6 ¹öÀüÀ» ´Ù¿î·Îµå ¹Þ¾Æ ¼³Ä¡ÇÏ¿©¾ß ÇÑ´Ù. ¶ÇÇÑ MAX+PLUS II BASELINE ¶óÀ̼¾½º ÆÄÀÏÀ»
¿äûÇÏ¿© ¼³Ä¡ÇÏ¿©¾ß ÇÑ´Ù. ¶óÀ̼¾½º ÆÄÀÏÀ» ¿äûÇϱâ À§ÇÑ ¸µÅ©´Â ´Ù¿î·Îµå ÆäÀÌÁö¿¡¼ Á¦°øµÈ´Ù.
2000³â 5¿ùºÎÅÍ ÀÌ À¥»çÀÌÆ®¸¦ ÅëÇÏ¿© MAX+PLUS II BASELINE 9.6 ¹öÀü¿¡¼ ¸àÅä
±×·¡ÇȽº»çÀÇ LeonardoSpectrumÀ̳ª ½Ã³ô½Ã½º»çÀÇ FPGA Express, VHDL ¹× Verilog synthesis ÅøÀÇ ¾ËÅ×¶ó
Àü¿ë ¹öÀüÀ» ¹«·á·Î Á¦°øÇÏ°Ô µÈ´Ù.
MAX+PLUS II BASELINE ´Ù¿î·Îµå ÆÄÀÏÀº 44,767,270 ¹ÙÀÌÆ®ÀÌ´Ù. ´Ù¿î·Îµå ¹Þ´Âµ¥ °É¸®´Â ½Ã°£Àº »ç¿ëÇÏ´Â ÀÎÅͳÝ
¾×¼¼½ºÀÇ À¯Çü°ú ÀÎÅÍ³Ý ¸ÁÀÇ È¥Àâµµ¿¡ ´Þ·ÁÀÖ´Ù. ¸¸¾à À¥ ºê¶ó¿ìÀú·Î ´Ù¿î·Îµå ¹Þ´Âµ¥ ¹®Á¦°¡ ÀÖÀ¸¸é FTP ÇÁ·Î±×·¥À» »ç¿ëÇÏ¿© ¾ËÅ×¶ó FTP »çÀÌÆ®ÀÎ ftp.altera.comÀÇ /pub/software µð·ºÅ丮³»¿¡
ÀÖ´Â ÆÄÀÏÀ» ´Ù¿î·Îµå ¹ÞÀ¸¸éµÈ´Ù. ¶ÇÇÑ ¸ðµç ¾ËÅ×¶ó ¹®Çå ¹× ÀÚ·á¿Í BASELINE 9.6 ¼ÒÇÁÆ®¿þ¾î¸¦ Æ÷ÇÔÇϰí ÀÖ´Â ¾ËÅ×¶óÀÇ µðÁöÅÐ ¶óÀ̺귯¸® CD-ROMÀ» ¿äÃ»ÇØµµ
(lit_req@altera.com¿¡ ¿äû) BASELINE ¼ÒÇÁÆ®¿þ¾î¸¦ ±¸ÇÒ
¼ö ÀÖ´Ù.
Note: ACEX 1K µð¹ÙÀ̽º¸¦ Áö¿øÇÏ´Â
MAX+PLUS II BASELINE 9.6Àº ¾ËÅ×¶ó µðÁöÅÐ ¶óÀ̺귯¸®
2000 Version 4ÀÌ»óÀÇ CD-ROM¿¡ Æ÷ÇԵǾî ÀÖ´Ù. ÀÌÀü
¹öÀüÀÇ ¾ËÅ×¶ó µðÁöÅÐ ¶óÀ̺귯¸® CD-ROM¿¡ ÀÖ´Â MAX+PLUS II BASELINEÀº
ACEX 1K µð¹ÙÀ̽º´Â Áö¿øÇÏÁö ¾Ê´Â´Ù.
ACEX 1K
µð¹ÙÀ̽º Áö¿ø°¡´É MAX+PLUS II BASELINE 9.6 ¹öÀü ´Ù¿î·Îµå ¹Þ±â |