Connecting ports by ordered list

• For Verilog gate primitives, the

first port on the port list is the output, followed by the inputs.
• <gate_name>
  • and
  • xor
• #delay - OPTIONAL
  • 2 time unit for the and gate
  • 4 time unit for the xor gate
• <instance_name> - OPTIONAL
  • u1 for the and gate
  • u2 for the xor gate
• (port_list)
  • (co, a, b) - (output, input, input)
  • (sum, a, b) - (output, input, input)

module half_adder (co, sum, a, b);

output co, sum;

input a, b;

parameter and_delay = 2;

parameter xor_delay = 4;

and #and_delay u1(co, a, b);

xor #xor_delay u2(sum, a, b);

endmodule

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