PPT 슬라이드
Instantiation of lower-level Components
- <component_name> - The name of your lower-level component
- #delay - The component delay
- Not required, used for simulation
- <instance_name> - Any name that you want
- Required, unlike Verilog gate primitives
- (port_list) - The port connection
<component_name> #<delay> <instance_name> (port_list);