Application of Registered Performance

• Use Registered Performance Analysis to see if design meets clock frequency requirement

• What to do if frequency is less than desired
  • Use List Path to display the worst case delays
  • Use Floorplan Editor to view the entire path
    • Are Logic Cells and pins scattered among different rows?
    • Can the Logic Cells benefit from carry/cascade chains (FLEX) or parallel expanders (MAX)?
  • Use Assignments ( Clique, Logic Options, etc… ) on the critical path to improve performance
  • If still less than desired, consider pipelining technique or different design implementations where appropriate

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