Device Timing

• Design considerations
  • Setup and hold times for signals coming on-chip
  • Clock-to-out for signals going off-chip
  • Maximum clock frequency, internal register-to-register performance

logic

clock-to-out time

logic

logic

setup time, hold time

clock frequency

D

Q

D

Q

이전 슬라이드

다음 슬라이드

첫 슬라이드로 이동

그래픽 버전 보기