PPT 슬라이드

Device Timing - Setup and Hold

tSU= data delay - clock delay + register setup time

tHOLD = clock delay - data delay + register hold time
• Register setup / hold time (see data book)
• Clock delay - depends on resource used
  • Dedicated Inputs drive global signals & PIA
  • I/O pins drive PIA
• Data delay - depends on
  • Resource used for data input
    • Dedicated Inputs drive global signals & PIA
    • Input pins drive PIA or macrocell registers directly via fast input path
  • Proximity of input pin and register

logic

D

Q

data delay

clock delay

이전 슬라이드

다음 슬라이드

첫 슬라이드로 이동

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