If FMAX Requirements Are Not Achieved...

• Identify the critical timing path in the design or the nodes/signals involved in the path

• “Clique” these nodes together using a clique assignment

• During recompilation, MAX+plus II will place the logic as close as possible together in the device

  • If possible, the logic is assigned to the same LAB
  • If logic will not fit into 1 LAB, the logic is placed in adjacent LABs on the same Row

• Make LAB or Row assignments using Assign -Pin/Location/Chip

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