Putting it all together

ENTITY cmpl_sig IS

PORT ( a, b, sel : IN bit;

x, y, z : OUT bit;

END cmpl_sig;

ARCHITECTURE logic OF cmpl_sig IS

BEGIN

-- simple signal assignment

x <= (a AND NOT sel) OR (b AND sel);

-- conditional signal assignment

y <= a WHEN sel='0' ELSE

b;

-- selected signal assignment

WITH sel SELECT

z <= a WHEN '0',

b WHEN '1',

'0' WHEN OTHERS;

END logic;

CONFIGURATION cmpl_sig_conf OF cmpl_sig IS

FOR logic

END FOR;

END cmpl_sig_conf;

이전 슬라이드

다음 슬라이드

첫 슬라이드로 이동

그래픽 버전 보기