DFF - clk=‘1’

sensitivity list only includes the

triggering signal, in this case, clk

clk = ‘1’ means that it is

positive-edge triggered

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY dff IS

PORT ( d : in std_logic;

clk : in std_logic;

q : out std_logic

);

END dff;

ARCHITECTURE behavior OF dff IS

BEGIN

PROCESS (clk)

BEGIN

IF clk = '1' THEN

q <= d;

END IF;

END PROCESS;

END behavior;