DFF - clk’event and clk=‘1’

clk is the signal name (any name)
‘event is a VHDL attribute,
specifying that there needs
to be a change in signal value
clk=‘1’ means positive-edge
triggered

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY dff_a IS

PORT ( d : in std_logic;

clk : in std_logic;

q : out std_logic

);

END dff_a;

ARCHITECTURE behavior OFdff_a IS

BEGIN

PROCESS (clk)

BEGIN

IF clk'event and clk = '1' THEN

q <= d;

END IF;

END PROCESS;

END behavior;