DFF with asynchronous clear

• This is how to implement asynchronous

control signals for the register

• Note: This IF-THEN statement

is outside the IF-THEN statement

that checks the condition rising_edge

• Therefore, clr=‘1’ does not depend

on the clock

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.all;

ENTITY dff_clr IS

PORT ( clr : in bit;

d, clk : in std_logic;

q : out std_logic

);

END dff_clr;

ARCHITECTURE behavior OF dff_clr IS

BEGIN

PROCESS(clk, clr)

BEGIN

IF clr = '0' THEN

q <= '0';

ELSIF rising_edge(clk) THEN

q <= d;

END IF;

END PROCESS;

END behavior;

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