XSI Design Flow

The “XSI Design Flow” figure illustrates the following required steps you follow to implement and simulate your HDL designs.

Refer to the “FPGA Compiler and Design Compiler Tutorial for XC4000E/L/EX/XL/XLA/XV Designs” chapter for step-by-step instructions on converting your HDL designs.

1. Use the Synlibs program to determine the appropriate libraries for your design.
   
   
2. Synthesize your design with either FPGA Compiler or Design Compiler.
   
   
3. Save your design as an SXNF file or an SEDIF file, along with a DC file that contains Synopsys constraints. Make sure you use the .sxnf file extension for FPGA Compiler designs and the .sedif file extension for Design Compiler designs.
   
   
4. Use the DC2NCF program to translate the Synopsys constraints DC file to a Netlist Constraints File (NCF).
   
   
5. Run NGDBuild on the SXNF or SEDIF file to create an NGD file.
   
   
6. Run the MAP program on the NGD file to create a mapped NCD file.
   
   
7. Run the TRACE program to determine if PAR meets your timing goals.
   
   
8. Run PAR on the NCD file to place and route your design.
   
   
9. Run TRACE again on your placed and routed design.
   
   
10. Run NGDAnno on your routed NCD and NGM files to create an NGA file.
    
    
11. Run either NGD2VHDL or NGD2VER on the NGA file to create a VHDL (VHD) or Verilog (V) file for simulation with the appropriate simulators for back annotation. These two programs also create a Standard Delay Format (SDF) file containing timing information.
    
    
12. Run the BitGen program to create a bitstream for programming the FPGA.
    
    

Figure 1.1 XSI Design Flow