IncludeNoTimingConstraint

The IncludeNoTimingConstraint command includes paths without timing constraints, in addition to paths with timing constraints, in analysis.

There is no direct equivalent menu command for IncludeNoTimingConstraint. The following three menu commands are associated with IncludeNoTimingConstraint:

• Report Paths in Timing Constraints (Analyze Menu)
  
  
• Report Paths Failing Timing Constraints (Analyze Menu)
  
  
• Report Paths Not Covered by Timing Constraints (Analyze Menu)
  
  

Syntax

The syntax of the IncludeNoTimingConstraint command is the following.

IncludeNoTimingConstraint {true|false}

• True reports paths with no timing concurrents (as well the paths with timing constraints). It is the default setting when opening a CPLD design.
  
  
• False does not report paths with no timing constraints. This argument is the default when opening an FPGA design.
  
  

Abbreviation

Abbreviate the IncludeNoTimingConstraint command syntax as follows.

intc {t|f}

Example

Following is an example of the IncludeNoTimingConstraint command.

includenotimingconstraint true